 In the multi-cycle synchronous bus protocol, the differences between the theoretical timing and the actual timing are pretty similar to those that we saw in the single-cycle synchronous bus protocol. Again, we've got some delay because our master and our slave are not in the same place as our clock. So there's a delay between when the clock cycle actually changes and when one of the devices sees that change occur. It also takes some small amount of time for those various changes to be made on the bus. We have to physically put the data on the bus, changing the voltage on those lines, and that takes just a little bit of time. Again, the slave is a little bit farther away from the clock than the master is, so all of the master's operations are finishing just a little bit sooner than the slave's operations. But the master knows once it sees the slave ready signal being asserted that this data is available and it has until the end of its clock cycle to go grab this data.