 Hello, and welcome to this presentation of the STM32 Interconnect Matrix. It covers the main features of this matrix, which is widely used to connect various internal peripherals between each other. The Interconnect Matrix, integrated inside STM32 microcontrollers, provides direct connections between peripherals. Applications benefit from these interconnections to ensure time predictable operations and decrease power consumption. This matrix avoids complex management of peripheral communications through reading or writing registers using CPU instructions. In some cases, it reduces the need to loop a signal from a source to a destination through a dedicated GPIO. The Interconnect Matrix offers two features. First, it ensures direct and autonomous connections between peripherals, allowing removal of latency in regards to software handling, thus saving GPIO and CPU resources. Second, the interconnection between certain peripherals can even operate during low power modes. The main peripherals having effect autonomous interconnections are connection sources, timers, analog IPs, clocks, extended interrupt event controllers, digital filters for Sigma Delta modulators, USB interfaces and system errors, and connection destinations, timers, analog IPs, digital filters for Sigma Delta modulators, and direct memory access controllers. Peripherals can be interconnected using the Interconnect Matrix even when the circuit is in a low power mode. The fully supported power modes are run and sleep. The connections from the real-time clock or GPIO to low power timers can also be used in stop modes, as well as Ethernet MAC, USB, low power timers, management data input output or MDIO slaves, real-time clocks, and the programmable voltage detector or PVD connection to the external interrupt event controller. The Interconnect Matrix can be used for synchronizing or chaining timers, allowing, for example, a master timer to reset or trigger a second slave timer. This slide shows a simple example of timer synchronization. Timer 3 is used as the master timer and can reset, start, stop, or clock Timer 2 configured in slave mode. Timer 3 is clocking Timer 2 so that it acts as a pre-scaler for Timer 2. Timers can also be triggered by a short circuit detection on a digital filter for Sigma Delta modulators when a USB start-of-frame is detected or by a real-time clock interrupt at a given time or at a regular interval. All these use cases are enabled thanks to the propagation of these triggering signals through the Interconnect Matrix. This example generates three-phase PWM signals in Timer 1. The commutation and duty cycle update are generated via the DMA engines, respectively Timer 3. The overcurrent is guarded by a comparator, external to the STM32 MP1 series, whose reference is driven by the Digital to Analog Converter, or DAC, and changed via the DMA engine. Phase voltage and currents are measured by an analog to digital converter, or ADC, which samples the channel four synchronously with the events generated by Timer 1. Other voltage sources are measured on external events, detected by the GPIO, and routed via the EXTI unit to the ADC regular trigger. The whole mechanism runs autonomously just after proper setup, so the CPU can safely execute speed or voltage regulation algorithms without the need for low-level control. The Interconnect Matrix is mostly used for triggering an ADC, DAC, or digital filter for Sigma Delta modulator through a timer event or an external interrupt, triggering a timer through an ADC or DFSDM watchdog signal, when a predefined threshold value is crossed by the analog input, triggering a DMA data transfer from memory to the DAC by a timer to allow a frequency-controlled conversion, calibrating HSI and LSI clocks, for example measuring the external oscillator LSE frequency by a timer clocked by the calibrated internal oscillator. Dual ADC mode, using ADC 1 as the master to trigger a start of conversion for the ADC 2 slave, monitoring the temperature of a connected internal temperature sensor or the VBAT to ADC voltage, or analog IP interconnect, for example DAC to an ADC, protecting timer-driven power switches through the direct connection of system error signals to the timer break input. These recommendations should be followed to ensure a proper interconnection in between the peripherals and avoid unexpected behaviors. Both peripherals need to be active and their inputs and outputs configured. When peripheral inputs share connections with other peripherals, associated GPIO alternate functions must be deactivated to avoid interference. Peripherals with active analog outputs override the associated GPIO functionality. Specific details can be found in the specific sections for each peripheral in the reference manual, as well as in the datasheet.