 Hello, and welcome to this presentation of the STM32 Display Serial Interface or DSI host. It covers the features of this interface, which is used for connecting graphical displays to the microcontroller. The DSI host integrated inside STM32 microcontrollers provides a high speed communication interface allowing the microcontroller to communicate with a display with a reduced pin count. This interface is fully configurable, making it easy to connect DSI displays available today on the market. Applications benefit from the easy connection and reduced pin count. The DSI host integrated inside STM32 microcontrollers offers three operating modes and is optimized for communication with graphical displays with a reduced pin count up to 1 gigabit per second. The number of data lanes is configured to exactly fit the application's needs. The DSI host is deeply integrated with the LCD TFT display controller or LTDC to ease application development and porting. Three operating modes are available to convey the graphical data to the display. Video mode streams over the high speed link the RGB data and the associated synchronization signals directly generated by the LTDC. The streaming starts as soon as the DSI host and the LTDC are enabled. This continuous refresh is the best way to interface with a display without graphics RAM or GRAM. APB command mode sends commands over the high speed link for configuration as it is done using a legacy serial interface, SPI or FMC. The commands are launched using the DSI host APB interface. Adaptive command mode is the best way to interface with a display having its own internal graphics RAM. The DSI host captures only one full frame coming from the LTDC and transforms it into a series of write commands to update the display graphics RAM. This one-shot refresh automatically sets a control bit in the DSI host. The DSI host video mode supports the three operating modes defined by the Mobile Industry Processor Interface or MIPI DSI specification. Non-burst with sync pulse where the synchronization signal and the data are sent accurately enabling the target display to reconstruct the original video timings including synchronization pulse widths without any buffering. Non-burst with sync event mode is similar to the previous mode but for displays not requiring synchronization pulse width information. Burst mode is the most energy efficient mode. RGB pixel packets are time compressed leaving time during a line transmission to go into low power mode or to transmit other commands. The DSI host must support all three modes. A display is only required to support at least one of these three modes. APB command mode is used to send commands through the DSI host APB register interface. Generic or display command set or DCS commands can be sent for display configuration at startup or for maintenance operations when the application is running. All the commands can be sent either in high speed mode or in low power modes as some displays only accept low power communication at startup. Commands can also be sent during video streaming. The DSI host scheduler automatically evaluates if it has the sufficient time to insert a command during a video transmission according to the program timings. All the commands are fully programmable by software which means the DSI host supports all the standard DCS commands and all the display specific custom commands. Speed command mode is a highly optimized operating mode to interface with displays having their own graphics RAM. It automatically refreshes the display's graphic RAMs or G-RAM with the LTDC without any load on the CPU or DMA controller. The graphics RAM refresh operation works in conjunction with the LTDC. The DSI host controls the LTDC and enables it for one frame. The RGB data coming from the LTDC are captured and are sent into a series of DSA long right command packets to the display. Once the graphics RAM is completely refreshed, the DSI host automatically stops the LTDC and the DSI link goes into low power stop mode. The user controls the refresh operation of the display by just setting one bit when the frame buffer is ready to be sent. The display can be refreshed at the maximum speed of the link so special attention must be given to the bandwidth requirement on the LTDC side. In other words memory bandwidth to read the frame buffer. The tearing effect allows a perfect synchronization between the display and the DSI host for refresh operations on displays having their own graphics RAM. The tearing effect can be signaled in two ways over the link without an additional pin or using an additional pin. When the tearing effect is signaled over the link, the DSI host sends a set tear on command and gives the control of the bus to the display. Once the program scan line is reached by the display, it sends a trigger to the DSI host and gives control of the bus back to the DSI host. An interrupt can be raised to launch the graphics RAM refresh. When the tearing effect is signaled over a pin, the display toggles a dedicated GPIO to trigger the DSI host when the program scan line is reached. Although an additional pin is required, this mechanism avoids having multiple exchanges over the link between the DSI host and the display. An interrupt can be raised on the pin, toggling the launch of the graphics RAM refresh. The choice between video or adapted command mode has a big impact on the solution's architecture and cost. From the MCU standpoint, adapted command mode is preferred for cost-optimized solutions. As video mode does not require graphics RAM on the display side, this solution is often used for large displays which reduces cost. The constraints in terms of bandwidth and memory usage on the MCU side remains the same as for today's LTDC-based solutions. Most of the time an external RAM is required for double buffering of the frame buffer. Adapted command mode requires a display with a graphics RAM. The display may have a slightly higher cost, but most of the display is smaller than 480 by 480 pixels embedded graphics RAM. As a consequence, adapted command mode with a small display will not always require an external RAM as the frame buffer may fit in the internal MCU RAM. This highly reduces the bandwidth issues on the MCU and reduces the overall bomb cost and solution integration as no external RAM is required. The DSI host supports video mode operation with timing accurate streaming, burst mode to reduce consumption during blanking periods, and several RGB color encoding formats to optimize bandwidth usage. The DSI host supports commands through its APB interface. DCS or generic commands can be issued to the display even when video mode is working. And commands are used for display configuration at startup and also for maintenance operations when the application is running. The DSI host can also use adapted command mode to update a display's graphics RAM without having to use the CPU or DMA controller. This mode works using the LTDC to transmit write commands to the display. In terms of performance, there is a relationship between the equivalent pixel clock and the DSI host configuration. Depending on the color coding, the number of data lanes used, and the speed of the data lanes, we can evaluate the equivalent pixel clock. As an example, when using two lanes at 500 megabits per second for a total of 1 gigabit per second, we have a maximum equivalent pixel clock of 62.5 megahertz for a 16-bit per pixel coding and 41.5 megahertz for a 24-bit per pixel coding. In terms of the application, we can have, for example, a small 400 by 400 pixel display running on a single 200 megabit per second lane at 16 bits per pixel or a large 800 by 600 pixel display at 24 bits per pixel running on both data lanes at 500 megabits per second each. The DSI host has many interrupts to monitor all timings and events of the communication. Please refer to the reference manual for a detailed description of all the interrupt sources. In addition to protocol-related interrupts, the DSI host also provides interrupts to manage regulator events, PLL events, and tearing effect events. As the DSI host uses the LTDC for data fetching, no DMA controller is necessary. The LTDC has its own DMA master. The DSI host is active in run and sleep modes. A DSI host interrupt can cause the device to exit sleep mode. In stop mode, the DSI host is frozen and its register content is kept. In standby mode, the DSI host is powered down and it must be reinitialized afterwards. Wearable applications require low power management functions together with a high-quality user interface. This can be achieved using the DSI host to interface with a display through only four or six pins. The low pin count needed to drive such devices allows for a highly optimized system integration. You can refer to the training slides related to RCC, interrupts, LTDC, and GPIOs for additional information.