 Hello, and welcome to this presentation of the STM32 General Purpose I.O. interface. It covers the general purpose input and output interface and how it allows connectivity to the environment around the microcontroller. General Purpose I.O. pins of STM32 microcontrollers provide an interface with the external environment. This configurable interface is used by the MCU and also all other embedded peripherals to interface with both digital and analog signals. Application benefits include a wide range of supported I.O. supply voltages as well as the ability to externally wake up the MCU from low power modes. General Purpose I.O.s provide bidirectional operation, input and output with an independent configuration for each I.O. pin. They are shared across up to seven ports named GPIOA to GPIOG. Each of them hosts up to 16 I.O. pins, except the 11 I.O. pins port G. I.O. ports support atomic bit set and reset operations through BSRR and BRR registers. I.O. ports are directly connected to the AHB2 bus in order to allow fast I.O. pin operations capable of changing every two clock cycles. Most of the I.O. pins are 5 volt tolerant. General Purpose I.O. pins can be configured into several operating modes. An I.O. pin can be configured in an input mode with floating input, input mode with an internal pull-up or pull-down resistor or as an analog input with optional pull-down. An I.O. pin could be also configured in an output mode with a push-pull output or an open drain output with an internal pull-up or pull-down resistor. For each I.O. pin, the slew rate speed can be selected from four ranges to ensure the best compromise between maximum speed and emissions from the I.O. switching and to adjust the application's EMI performance. I.O. pins are also used by other integrated peripherals to interface with the external environment. Alternate function registers are used to select the configuration for the peripherals in this case. The configuration of the I.O. ports can be locked to increase application robustness. Once the configuration is locked by applying the correct write sequence to the lock register, the I.O. pin's configuration cannot be modified until the next reset. Several integrated peripherals such as the USART, TIMERS, SPI and others share the same I.O. pins in order to interface with the external environment. Peripherals are configured through an alternate function multiplexer, which ensures that only one peripheral is connected to the I.O. pin at a single time. Of course, this selection can be changed during runtime of the application through the GPIO-X AFRL and AFRH registers. The configuration of any I.O. pin is achieved through four registers GPIO-X MODE-R GPIO-X O-Type-R GPIO-X O-Speed-R GPIO-X PU-PDR Register GPIO-X MODE-R selects the functionality of the I.O. pin, digital input, digital output, digital alternate function or analog. Register GPIO-X O-Type-R is relevant when the pin is in output. It selects open drain versus push-pull operation. Register GPIO-X O-Speed-R selects the speed of the signal received or transmitted by the pin. Register GPIO-X PU-PDR enables and disables pull-up and pull-down resistors. During and after reset, the alternate functions are not active. Only debug pins can be used in alternate function mode. JTAG and serial wire debug pins remaining in alternate function configuration mode are listed in this slide. When the external oscillator is switched off, pins related to this oscillator can be used as standard I.O. pins. This is the default state after a device reset. When the external clock source is used instead of a crystal oscillator, only the related OSC-in pin is used for the clock and the OSC-out pin can be used as a standard I.O. pin. This slide explains the legend and abbreviations used in the pin-out table present in the STM-32G4 datasheet. FT means 5 volt tolerant and TT means 3 volt tolerant. A suffix further describes the I.O. pin. UNDERSCORE-A means analog. UNDERSCORE-C means USB type C, power delivery capable. UNDERSCORE-D means USB type CPD, dead battery function. UNDERSCORE-F means fast mode plus capable. For instance, an FT-UNDERSCORE-FA pin is 5 volt tolerant supporting an analog configuration and also a digital configuration with fast mode plus. I.O. pins remain active in all modes except standby and shutdown where the only available configuration is input with internal pull-up, pull-down resistor or floating input. When exiting shutdown mode, the I.O. configuration is lost. When the MCU is under reset, I.O. pins are forced into an analog input mode. When the microcontroller is unpowered, it still presents the dead battery RD pull-down, provided that UCPD, DBCC1 and UCPD, DBCC2 pins are each connected to UCPD, CC1 and UCPD, CC2 pins respectively. Since JTAG, TRST and UCPD, CC2 are multiplexed on the PB4 pin, it is not possible to use JTAG and dead battery signaling at the same time. For non-dead battery applications, JTAG is available on the condition that PB4 state is not pulled down. This can be achieved by either pulling down the DBCC2 pin or connecting an external pull-up on PB4. Software can disable the dead battery signaling by setting the UCPD1, db-dispit in the PWRCR3 register. PB8 may be used as boot pin called boot zero or as a GPIO, depending on the SW boot zero bit in the upper option byte. It switches from the input mode to the analog input mode. After the option byte loading phase, if n SW boot zero equals one, after reset, if n SW boot zero equals zero. So PB8 boot zero is not a dedicated pin. It can be used during reset time to select the boot mode and can become a general purpose IO during the runtime. PB8 GPIO is available by default because the production value of the n SW boot zero option bit is zero. PG10 may be used as reset pin called NRST or as GPIO, depending on the NRST mode bits in the user option byte. It switches to those mode. Reset input output, default at power on reset or after option bytes loading NRST mode equals three. Reset input only after option bytes loading NRST mode equals one. GPIO PG10 mode after option bytes loading NRST mode equals two. Reset input output is available by default because the production value of the NRST mode option bits is three. This table shows the differences with the STM32L4 microcontroller. Analog with pull down is a configuration which is supported the STM32G4, but not by the STM32L4. Note that the STM32G4 also supports the analog mode without pull down. The purpose of this analog plus pull down capability is to force a low level on the pin when the external analog line is disconnected in order to avoid a floating state. For more details about the system configuration module, refer to the reference manual for STM32G4 microcontrollers. Refer also to these trainings for more information if needed. USB Type-C power delivery or UCPD, debug or dbg