 Hello, and welcome to this presentation of the STM32MP1 hash processor. The hash peripheral is in charge of efficient computing of the message digest. A digest is a fixed-length value computed from an input message. A digest is unique. It is virtually impossible to find two messages with the same digest. The original message cannot be retrieved from its digest. Hash digests and hash-based message authentication code, or HMAC, are widely used in communications since they are used to guarantee the integrity and authentication of a transfer. Hash 1 is a secure peripheral under ETZ-PC control through ETZ-PC-DECPROT-0-BIT-8, while hash 2 is a non-secure peripheral. The hash 1 instance can be allocated to the ARM Cortex-A7 secure core to be controlled in OPTI by the hash OPTI driver, or the ARM Cortex-A7 non-secure core for using in Linux with Linux crypto framework. The hash 2 instance can be allocated to the ARM Cortex-M4 core to be controlled in the STM32 cube MPU package using the STM32 cube hash driver. The hash 1 instance is used as a boot device to support binary authentication. The hash processor supports widely used hash functions, including message digest 5 or MD5, secure hash algorithm SHA1, and the more recent SHA2 with its 224 and 256-bit digest length versions. A hash can also be generated with a secret key to produce a message authentication code, or MAC. The processor supports BIT, BITE, and half-word swapping. It also supports automatic padding of input data for block alignment. The processor can be used in conjunction with the DMA for automatic processor feeding. Digest computation can be either partial each time the FIFO is full or final, no more bytes to add. The application shall manage the final digest differently depending on the case. A single DMA transfer, MD-MAT-BIT0, multiple DMA transfers, MD-MAT-BIT1, or any transfer with MDMA hash 1 only. All supported hash functions work on 512-bit blocks of data. The input message is split as many times as needed to feed the hash processor. Subsequent blocks are computed sequentially. MD5 is the less robust version with only a 128-bit digest. The SHA standard has two versions, SHA1 and the more recent SHA2, with its 224 and 256-bit digest length versions. MD5 and SHA1 are not qualified as secure digests according to NIST. The hash-based message authentication code, or HMAC, is used to authenticate messages and verify their integrity. The HMAC function consists of two nested hash functions with a secret key that is shared by the sender and the receiver. The hash function involved in the HMAC computation can be any one supported by the peripheral. MD5, SHA1, or SHA2. The hash processor complies with the international standards for secure hash algorithms, or SHA, message digest algorithms, or MD5, and for keyed hash, message authentication code, or HMAC. This simplified block diagram of the hash processor shows the basic data flow and control modules. The hash processor processes 512-bit data blocks and generates digests of up to 256 bits depending on the algorithm. Input data may be swapped before entering the core unit, where they will be processed, to generate a simple hash or a message authentication code, or MAC. An interrupt in the nested-vectored interrupt controller, or NVIC, is triggered when a hash digest has been successfully calculated, or when the hash processor is ready to accept a new block of data. In direct memory access or DMA mode, requests are generated internally for incoming data. The DMA channel must be configured in memory to peripheral mode, with a data size equal to 512 bits. Single or fixed burst requests, so four words are supported. These are the times it takes top process a single block of data, depending on the chosen algorithms. HCLK is the CPU clock, and can go as high as 216 MHz. Note that the main benefit of using a hardware accelerator is to increase speed and save power, compared to a full software implementation of the hash functions. Compared to the processing of an intermediate block, it can be increased by the factor below. 1 to 2.5 for a hash message, around 2.5 for an HMAC input key, 1 to 2.5 for an HMAC message, around 2.5 for an HMAC output key, in case of a short key, 3.5 to 5 for an HMAC output key, in case of a long key. Here is an overview of the status of the hash processor in each of the low power modes. Hash operations are not possible when the device is in stop and standby modes. This is a list of peripherals related to the hash processor. Refer to training on the DMA peripheral for information on how to configure the hash channel. And please refer to Crip Training if you want to know more about cryptographic engines. For more details, please refer to this user manual available on our website.