 Good morning everyone. So, today we are going to start with sequential circuit and let us see how it goes. If it gets over early, I wanted to actually talk about some other topics as well. So, sequential circuits of course start with a latch and we will come to this latch earlier, but before that let us just go through a little bit of motivation for the students. Why do you want to study sequential circuits? How are they different from combinatorial circuits? So, the digital circuits we have seen so far and that was yesterday, gates multiplexers, demultiplexers, encoders, decoders, etcetera. They are all combinatorial in nature and what does that mean? That means the outputs depend only on the present values of the input and not on their past values. So, in other words these circuits really do not have a history or a memory embedded in them and that is why they are called combinatorial circuits. This just depends on what combination of inputs you apply at the input and does not matter in what sequence you apply those. So, that is why they are called combinatorial circuits. In sequential circuits, the state of the circuit is crucial and you know all that in a JK flip flop for example, its output will depend on what it was, what the state was in the earlier before the clock came. So, the state of the circuit is crucial in determining the output values. For a given input combination, a sequential circuit may produce different output values depending on its previous state. So, in that sense the sequential circuits have a memory. So, in other words the sequential circuit has a memory of its past state whereas, the combinatorial circuit has no memory. So, that is the basic difference between sequential circuits and combinatorial circuits. All right, why do we want to bother with sequential circuits because they are just about everywhere. Sequential circuits together together with combinatorial circuits make it possible to build several useful applications such as counters, registers, arithmetic logic unit that is ALU all the way to microprocessor. If you look at a microprocessor, it has got the clock is a predominant part of a microprocessor and the clock is there because there are lots of sequential circuits inside including the program counter and so on. All right, so let us get back, let us get to the most basic block of a sequential circuit and that is a latch and a latch you can make either with a with NAND gate or with NOR gate and this is called an RS latch and let me just what I will do is I will just work this because the resolution price probably not good enough for you. I will just write this on the paper and let us go from there. So, we have this latch and the difference between these and what we have seen in the combinatorial circuits is immediately clear that there is a feedback path from the output to some inputs and that is what makes this circuit have memory. Now, what is R, what is S, what is Q, what is Q bar? One approach is we tell we say that this terminal is R, that terminal is S and Q and Q bar and so on, but that is not very satisfying. So, what I am going to do is I am going to call these some arbitrary names A and B, I am going to call this Q and I am going to call this Q bar. So, now let us see what happens if I apply certain combinations of A and B. So, the first combination I take is A equal to 1, B equal to 0. Now, very often it is possible to just take this entire table without actually showing why what is what and why how it comes about, but of course, as I said it is not very satisfactory. It is always good to since the students already know about NAND gates, it is always good to explain to them that this is indeed what you will expect and not just state it. So, A is equal to 1, B equal to 0 and if B is 0 immediately we have Q bar equal to 1, this is Q bar, we have Q bar equal to 1. If Q bar is 1 that is getting fed back over here. So, we have 1 here, 1 here and that is why here 0 here. So, this entry of the table we can complete just based on NAND gates without actually knowing what this table is going to be beforehand. So, it is always good to start from the basics in that sense, 0. Let us take A equal to 0, B equal to 1 now and we can show that this is going to be 1 and this is going to be 0. What about A equal to 1, B equal to 1? Now, this state is sort of tricky because this is something that the students are coming across for the first time and what. So, let us let us worry about just this part and let me just circle this A equal to 1, B equal to 1 and let me get rid of this. So, in this case let us see if 0, 1 is possible. So, if this is 1 that 1 goes here this is also 1. So, this is 0, this is 0 and therefore, this is 1. So, this state is possible. So, 0, 1 is possible and by the same procedure we can also show that 1, 0 is possible as well. So, 0, 1 is possible, 1, 0 is possible. So, which one of these things will prevail? So, that depends on what these things were in the past. So, we say previous. Note that so far we have not even talked about the clock, but the clock we should bring in at some point. It is best not to bring it in the beginning because the idea of this latch is independent of the clock as such. The clock is just a synchronizing convenience that we add later on. So, it is always good to describe this just this latch. And so in that sense this circuit has latched in these previous value. If your inputs are going to be 1, 1 this previous value gets latched in forever unless now there is some change in A and B. What about 0, 0? If these are both 0 then q will become equal to 1 and q bar will also equal to 1. And as you know this state actually we do not allow. Why do not we allow that? First of all is q and q bar are not complementary that is just one of the reasons, but there is another very important reason that we will come to little later. Now, just looking at this table now we need to figure out why what we should call A and what we should call B. So, here what we are we need to introduce the concept of a latch getting set and latch getting reset. All these things remember that this point the student has not really heard. So, even when you say set we already know what it means but the student does not know. So, latch getting set means q is becoming 1. Latch getting set means q is equal to means q is becoming 0. So, now knowing this now we need to figure out what values of A and B will set the latch, what values of A and B will reset the latch and then we can figure out what A is and what B is. So, if you notice A is 1 if A is active and B is not active the latch is getting reset. So, therefore, A must be the R input similarly if B is active A is not active the latch is getting set. So, therefore, the B must be the S input. So, instead of just writing R S in the beginning it is always better to write call these some arbitrary names A and B and show that this indeed must be R and this indeed must be as much more satisfying for the student perspective. So, instead of just giving the student some magic table it is better to derive that table from first principles. So, the important point two important points here this 1 1 input gives you a previous it gives you the same state as the previous one. In other words the latch continues its previous state and this 0 0 is not allowed and we will come back to this 0 0 business a little later. So, let us get back to this slide. So, this slide is nothing but what we have just discussed just a continuation of the same thing. So, at the end of this slide we say that the input is therefore, called the reset input or R input and B is called set input. So, let us consider this further and maybe again you the resolution problem would be there. So, I will just draw this on paper this way form. So, the important thing is why do not we allow this R equal to 0 S equal to 0 entry. So, let us take another look at that. So, here we have the latch this is R this is S. So, we have we have seen earlier R is 1 S is 0 Q is B set R is 0 S is 1 Q is set 1 1 previous state and 0 0 not allowed. Now, so this is the entry that we want to look at in some more detail and see why is it not allowed. So, let us take some way form I am going to plot R S Q and Q bar. So, let you have all this in your slide, but let me just draw it here because you are not able to see this is R given this is S also given and we are given that this input Q is 1 in the beginning and Q bar is 0. So, the transition points are these transition transition points means the points at which things may change may or may not change. So, let us let us start with this point S S is 1 R is 0. So, therefore, Q is 1 and that will continue all the way up to here. Now, when we cross this S is S and R are both becoming 1 and the latch will just hold on to its previous state and all this time of course, Q bar is actually 0 Q bar is 0 at this point what happens is R becomes 1 S becomes 0. So, therefore, the latch gets reset it is always good to work this out in class. So, the students have some idea about the applications immediately comes of the actual time domain. So, let me extend this a little bit further we are now going to the next slide, but that is let me just write it here after this R and S are both become 1. So, this will continue its present state is also Q bar will also continue and at this point let us say R and S both become 0 R S become 0 S S become 0 and at this point let us say R and S become 1 1 again 1 and. So, now it is very clear like we said before at if we have 0 0 here definitely the gate outputs are both going to be 1. So, here we have a 1 and here we have a 1. So, that is a state of affairs at this point. Now, at this particular time instant R and S are both going to 1 now the question is what should we take as the previous state big question. Now, there is no unique answer to that and what will happen finally is the flip this latch will either reach the state Q equal to 1 or Q equal to 0 depending on the internal delays of these 2 9 gates and that of course, is. So, there is a big question mark here what will happen next and this kind of uncertainty of course, we do not like in digital circuits at all because we would like for a known set of inputs you would like known outputs. So, therefore, this is not allowed. So, yeah this figure is not looking quite all right, but if you look at the slides you will see it much better. So, that is the reason R and R equal to 0 S equal to 0 is not allowed. So, let us get back to the document and this slide will essentially just have done just now. So, at this point we have this question mark which we do not like. There is a NAND gate NAND latch similarly, we can make a NAND latch and once again we can instead of calling this R and S we can actually call it A and B force and show that this will turn out to be R this will turn out to be S and so on. So, I have not shown all of those figures, but you can do that in on the board if you like when you teach. So, in this case that things are pretty similar R is 1, S is 0 will reset the flip flop or the latch R is 0, S is 1 will set the flip flop or set the latch. There was a question on Moodle yesterday about what is the difference between a latch and a flip flop. So, we will come to that, but essentially latch can have a level clock level. So, latch is the level trigger device whereas, a flip flop is an H trigger device that is the difference. We will come back to this point later. So, this latch is the first two entries are identical. Now, in this particular case R equal to S equal to 0 will give you the previous state whereas, R equal to 1 S equal to 1 is invalid. So, in this in the last two entries it is different than the NAND latch. It is important to point this out and in fact it is even better to have these together at the same point. So, that the students can compare the first two entries 1 0 latch is reset 1 0 the latch is reset 0 1 the latch is set 0 1 latch is set. So, these two are identical and the next two entries are actually different. So, here 1 1 gives you the previous state here 0 0 gives you the previous state. So, it is good to put this together so that the students have a ready reference for making out the difference and similarities between these two latches. It is good to point out an application of this RS latch and in electronics if you have a mechanical switch there is something called chatter or bouncing and it is an RS latch that can actually help in preventing that from happening. The resolution may be a little low here for you. So, I will leave this to you can just go through this slide and you can. So, this is what happens in a latch you can probably see this graph at least. So, what we are doing is V o versus T in this figure what we are doing is there is a switch here which goes from this position A to position B. So, and at B we have this voltage source and at A we have this ground. So, the expected output voltage is 0 up to this point and at T equal to 0 the switch goes to position B and therefore, it should be the source voltage at this point. What actually happens in practice is that there is some chatter and then the switch position will actually be will not immediately go to one, but there will be some moments when it is actually in the air not connected anywhere. So, and that will show up as a 0 volt in this V o versus time if you expand this on the millisecond scale. Now, this is the chatter that we want to avoid for example, if you are feeding this to a counter you will actually be counting erroneously. You will be counting more what you should count. So, this is the chatter that we want to get it off and an RS flip flop can actually help in this way. So, what we have done here is this part is the same E and D this is 5 volts this is also 5 volts and the ground is connected to the center of the switch or the pole of the switch. And then we have an RS flip flop and that is the table that we have seen before and I guess this is the NAND latch because we have 1 1 showing as the previous Q. So, what happens is now this S and R inputs will have this bouncing effect. So, S will go like that R will go like that, but because of flip flop properties when S is 1 and R is sorry when R is 1 and S is 0 the flip flop is 0 and when become when S becomes 1 and R becomes 1 the flip flop latch actually does not change it remains 0. Similarly, when S is 1 this R is undergoing some bouncing and so that gives you either R equal to 0 or R equal to 1. So, the moment R becomes 0 the flip flop the latch will get set and R equal to 1 S equal to 1 actually does not cause any problem because here is just in the previous state. So, therefore, you still have the latch will retain its previous state and therefore, this will remain 1. So, now you have a clean transition from 0 to 1 that is how you can these things are actually used in digital circuits if you are comparing some things and based on that driving some further circuit this is a good latch to have. So, it is good to just point out an application to students at this point right the clock why do we need the clock. So, it is because complex digital circuits are generally designed for synchronous operation because it just makes the design procedure much easier that is transitions in with the various signals are synchronized with the clock. So, what is the clock it is basically it serves to synchronize the various operations in a microphone or in a complex digital circuit and why do we worry about synchronous circuits because they are easier to design and troubleshoot because the voltages at the nodes both the output nodes and the internal nodes of the circuit can change only at specific time that is why it is all of all of these processors will have a clock signal. The clock is a periodic signal with a positive going transition and a negative going transition. So, now this periodic does not mean that it has to be it has to have a duty cycle of 50 percent it can have different duty cycle. But the important thing is that each clock cycle has a positive going edge and a negative going edge. So, since the students are not really come across these words at this point it is good to point out that there is such a thing called a positive going edge in which the clock goes from 0 to 1. There is such a thing called negative going edge in which the clock goes from 1 to 0. And the clock frequency of course is extremely important because it determines the overall speed of the circuit. For example, a processor that operates with 1 gigahertz is 10 times faster than one that operates with 100 megahertz. And of course we have seen this revolution in processor what in 10 years ago we probably did not even have 1 gigahertz processor. Now, we have already more than 2.5 or whatever and the computer therefore the speed the things that you can do with your computer now have a change. So, now we come to a clocked RS latch and of course you are all familiar with this. So, although you cannot probably view this although this resolution may be a slight problem I hope you can at least see this figure clearly. So, this is our previous latch and now I call this A and call this B and not R and S. So, let me explain why let me just go back to the paper. So, here is our NAND latch the old one this is connected to another NAND gate. So, this is your clock and as I said this is a latch clock latch and it is sensitive to the level of the clock and not the edge as flip-flops are. This is our old friend the NAND latch and now I am going to not call this R and S, but A and B because I would like to have my R and S outside this bigger box this is still Q this is still Q bar. So, this box is the latch that we have seen before this is the actual clocked latch. All right why did we call this A and B because we want to now name these things as R and S and we do not let us see which one is which. So, for about this inner box the NAND latch we already know this we know that if A is 1 and B is 0 Q is 0 Q bar is 1 if A is 0 B is 1 Q is 1 Q bar is 0 if A is 1 B is 1 then this is previous and then 0 0 is not allowed. Now, if clock is 1 then let us call this X and Y if clock is 1 this A is actually X bar and B is Y bar. Now, remember this A is serving as the reset input and B is serving as the set input. So, therefore, X bar is serving as the reset input and Y bar is serving as the set input. So, in other words if you want to name these things we should actually name this as S and R right. So, this should be S and this should be R and then your overall flip flop if clock is equal to 1 will look like this R S then it will follow the same table as before. So, R is 1 S is 0 the flip flop gets reset R is 0 S is 1 the flip flop R is alright here is here is the point that we need to worry about what happens if R is 1 S is 1 what happens is R is 0 S is 0 if R is 1 S is 1 then A and B actually become 0 0 and that is not allowed. So, now the not allowed state is not 0 0 but 1 1 0 0 if S is 0 R is 0 this A and B will become 1 1 and that that corresponds to this entry of the latch table and then we have the previous state whatever clock equal to 0 clock equal to 0 means A and B are both equal to 1 and therefore, the there is no change and therefore, as long as clock is 0 this latch does not change its state and clock equal to 1 makes things happen. So, that is why this is a level sensitive latch. So, again it is important to actually convince students that this must be the S S terminal and this must be the R terminal rather than just stating it alright let us go ahead. So, that is what this slide is talking about alright and then there are some terms here which will be based which are based on the table that we just derived and a given R and given L. So, here is a clock signal if you cannot view it too clearly you can just get back to this slide later and see what what it is doing. So, if clock is 0 you can see that no change really happens. So, the previous queue will actually continue whether you are here or here or here and so on the same queue will continue. So, the previous value of queue will just continue when clock is high then the output will output can change depending on what R and S are. So, at this stage it is always good to show some waveforms to the students. So, that they can connect this latch with you know some real circuit operation rather than just going ahead with more and more loss and boring. So, it is better to just let them think a little bit about what happens in the time domain. H trigger flip flops. So, this is the difference between flip flops and latches flip flops are H trigger. So, the clock R S latch seen previously is level sensitive that is if the clock is active the flip flop output is allowed to change depending on the R and S input we have already seen that and we have seen an example of the waveforms. In an H triggered flip flop it is sensitive flip flop the output can change only at the active edge of the clock. Now, the active edge will depend on what kind of flip flop it is there are flip flops which are triggered by positive edges there are flip flops which are triggered by negative edges. So, here is an example. So, an R S an H triggered R S flip flop will be denoted by this little triangle here that means H triggered and if there is a circle outside this triangle then that means it is a negative H triggered flip flop. So, this nomenclature is something that the students must understand very well. Now, the table of a JK flip flop. So, what is a JK flip flop here is a simple first circuit of a JK flip flop and we will later find that there are some problems with this circuit and since again this is the font is small let me just write this here on the paper. So, we have the same NAND latch as we discussed before these are Q this is Q bar. Now, this is the input of this latch is coming from other NAND gate then there is a clock input then there is a J input and there is a K input and then there is some feedback involved. So, this Q bar is actually fed to this first NAND gate Q is fed to this second NAND gate and this whole thing is then called the JK flip flop. Why are we doing all this taking all this trouble because there is a point that is to be made. So, let us fill up some of these entries clock J K and Q N plus 1. Now, Q N plus 1 means the N plus 1 at clock pulse. So, if clock is 0 what do we have we have one here and we have one here and then of course, we know that this latch will keep its present state previous state. So, it does not matter what J is it does not matter what K is and this holds on to its previous state. In other words, it is the same as what Q N was. What if the clock is 1 and this is 0 and this is 0 J is 0 K is 0 and this is still 1 and this is still 1 all the clock is 1 and this will still hold on to its previous state what about 1 0 1 now you can. So, this is clock is 1 J is 0 K is 1 you actually can then work out what will happen this 0 will immediately force a 1 here and then you can take two possibilities and actually show that all this is done in the slide and just go through this details we can we can show that this will become 0 for clock high this 1 J equal to 1 and K equal to 0 this will become 1 what happens if clock is 1 J is 1 and K is 1 that is an interesting case. So, this is this is 1 this is clock is 1 and J is also 1 all right. So, now what will happen is if your Q bar was let us say Q bar was 0 this will become 1 and if your Q was. So, if Q bar was 1 Q would have been 0 sorry Q bar was 0 Q would have been 1 and this would become 0 this will give you Q bar becoming 1. So, Q bar earlier was 0 and now it is becoming now it is becoming 1. So, you can explain this in class take spend some more time for the students. So, essentially you can show that this toggles right and that is a new entry. So, previously we were not allowing these kinds of things here we were saying things not allowed and so on, but now in this particular flip flop we are actually allowing it ok. But what the problem here in with this flip flop is that if J is equal to K is equal to 1 right we have seen that it has toggled, but now what happens J and K are still 1. So, it will toggle again ok. So, let us say this it was 0 first Q equal to 0 then it became 1 again it became 0 again it become 1 and so on. So, as long as J and K are 1 this will simply go on toggling and that is what we do not want. So, therefore, this circuit actually has to be improved and that actually has led to the master slave configuration. So, you need to now the master slave configuration is a little too difficult to sort of cover a basic course because there are too many cases to consider and so on, but the motivation for that at least should be brought out by showing this detail ok. So, that is what is done in this slide what we just did on paper ok. So, here is an important point consider J equal to K equal to 1. So, as long as the clock is 1 Q will keep toggling and that is something that we do not like what is the frequency the frequency will depend on the delay values of the various case involved ok. So, that is something that we do not want. So, therefore, we improve on this and that leads us to the master slave configuration. You can just show the master slave configuration in class perhaps, but actually analyzing it will take you a long long time and I am not sure it is not clear whether it is really worth it at this level. So, you could just say that ok this master slave configuration the basic operation of the master and slave is like that is when this clock is 1 then this latch is active, but this latch is still not affected and only when the clock becomes 0 then this comes into picture and therefore, this whole operation this whole flip flop becomes sensitive to an edge and it also gets rid of this problem that we just saw. So, the in the table you will see that instead of clock equal we have written a downward edge I hope it is sort of visible to you. There is a downward edge here rather than saying 0 or 1 and that is the active edge and that is when things can happen ok. So, note that unlike the R S 9 latch which does not allow one of the combinations of R and S that was R equal to S equal to 0 the J K flip flop allows all four combinations and that is a very big difference between J K and R S. Since the students are looking at this for the first time it is important to emphasize this point ok. Positive edge triggered and negative edge triggered flip flop the transition tables are basically identical except the active edge here is positive the active edge here is negative and of course, the symbols are different here we do not have the circle for the clock here we have the circle for the clock because it is the negative edge that is active edge ok. Now, this is a very very important point and let us go through this slide in detail. So, consider a negative edge triggered flip flop that is shown here. So, as we have shown earlier this flip flop has got a master latch and a slave latch and the master gets clock whereas, the slave gets clock bar right. Now, consider a clock like that. So, as seen earlier when clock is high the input J input J and K determine the master latch output Q right. So, that means Q 1 rather. So, this Q 1 is then determined by what are these inputs J and K and all that will happen when clock is 1 right. Now, since clock bar is 0 this slave output actually is not affected you do not see any output you do not see any change there is a change in Q 1, but that is not reflected in the output Q. So, during this time no change is visible at the flip flop output Q very important. When the clock goes low the slave flip flop becomes active. So, now the master is inactive and the master has already done his job it has changed Q 1 and Q 1 bar according to what J and K were and now the master has become inactive. So, no changes will happen in master because the clock is gone to 0 clock bar is gone to 1. So, therefore, this changes that were effect that were performed by the master will can now reflect in the flip flop output Q and Q bar. So, when the clock goes low the slave flip flop becomes active making it possible for Q and Q bar to change alright. So, the important point is that in short although the flip flop output Q can only change after the active edge right what is the active edge here the active edge is the negative edge. The new Q value is determined by J and K values just before the active edge and why is that because just. So, this master has actually done his job just before the active edge right and that is why so the master will only look at J and K values just before the active just before the active edge after the active edge the master actually is inactive it does not do anything. So, therefore, in order to determine the flip flop values Q and Q bar we need to look at what was J and K just prior to this active edge that is very important. I have seen students making all kinds of mistakes in the examinations and so on if they do not get this right this is a very important point cannot really over emphasize that very very important point at this point it is good to give some waveforms. I hope you can at least see the waveforms if not all these details. So, there is a clock here there is J and K some sample values and it shows what Q looks like and this is a positive edge triggered flip flop. So, things will change only at the positive edge of the clock. So, J is 1 here K is 0 here. So, therefore, Q has become 1 remember we are always looking at what happens just before the active edge right. So, the active edge is positive going. So, we are looking at J and K values just before the positive edge here at the next positive edge. So, nothing happens before the next active edge comes along here at this point and just prior to that J was 0 K was 0 and therefore, the flip flop continues to hold it straight next active edge J is 0 K is 1. So, therefore, the flip flop has changed its state to 0 next active edge just before the next active edge J is 1 K is 1 and therefore, the flip flop has doubled and so on. So, if you show a figure like this at this point it really has to fix this table in the student's mind otherwise it just remains a table which has to be sort of mugged up and reproduced in the exam is not a satisfactory approach. Now, the same inputs, but now the flip flop is negative edge triggered then what happened. So, you can go through this now things are things get aligned with the negative edge of the clock rather than the positive edge and otherwise since the inputs are actually similar the output will not really change much, but this is an important difference. These changes in the output here are aligned with the positive edge of the clock here it is here it is aligned with the negative edge of the clock there is a difference between positive edge and negative edge triggered flip flops. So, here is an example that we have worked let us do this on paper and just see in general how to go about analyzing this J k circuits involving J k flip flops. So, let me just reproduce this figure on paper. So, there are there is a simple circuit consisting of two flip flops and they are positive edge triggered. So, this we will call as let me call this as J 1 J 2 sorry K 1 J 2 K 2 Q 1 Q 1 bar Q 2 Q 2 bar. Now, the clock is the same for both flip flops and let me show that here it is driven by a common clock both of these are common clock. So, this is the clock in this in case of the first flip flop J 1 and K 1 are both tied together and they are tied to 1. So, they are equal to 1 J 2 and K 2 it is like this. So, we have J 2 which is connected to Q 1 bar we have K 2 which is connected to Q 1. So, there is a clock which is common that we already shown J 1 K 1 are both connected to 1 J 2 is coming is the same as Q 1 bar J K 2 is the same as Q 1 and that is it and we are asked to find what will happen to Q 1 and Q 2 as time goes. So, let us say we are given that Q 1 and Q 2 is equal to 0 to begin with and we are asked to find what happens in the next few cycles. So, I want to do this in detail because if you do a similar problem in class in detail the students will really benefit from that and it is not always easy especially if there are more complex connections it is not always easy to figure out things unless you do it systematically. So, let us just see how to go about this very very systematically. So, we write at the table here for the J K flip flop first J K Q. So, 1 0 we know the flip flop we get set 0 1 get 3 set 0 0 same as Q n 1 1 Q n bar. So, this when you are doing this kind of a problem 1 on board it is always good to write this thing in the corner of the board. So, that for reference. So, that is our table and we are going to continue to report to this as we go along. So, what do we do next? So, let us draw the timing diagram. So, this is our we are going to draw three things one is the clock and so on then we will draw Q 1 and that is something that we have to figure out what it is and then we will draw Q. So, this is the clock here Q 1 and then we have Q 2 and we are given that to begin with we have Q 1 is equal to 0 and Q 2 equal to 0. Now, let us see how to go about this little complex because there we have this kind of connection here and it we need to really figure out what is happening to J 2 and K 2 every time the clock active clock clock edge comes. So, let us start like this let us tabulate the values of J 1 K 1 J 2 K 2 and then Q next or Q n plus 1. If you do this systematically and there is no way you will make you are the students will make any mistake and that is how we should really do this. So, J 1 and K 1 are actually always one. So, in fact we can fill up this table even without looking at the outputs Q 1 and Q 2. Here we of course need two of these because there are two flip flop. So, Q 1 n plus 1 and Q 2 n plus 1. So, even without looking at this Q 1 Q 2 column we can fill up J 1 K 1 because they are always try to one. So, what is going to happen Q 1 is something that we can draw even without looking at Q 2 because there is no connection of Q 2 with the first flip flop. So, it is simply going since J equal to 1 K equal to 1 we are at the last entry of this table and it is simply going to toggle keep toggling irrespective of what is happening at the Q 2 and so on right that is given that we do not really need to think much about. Now, the output of the second flip flop will depend on what Q 1 and Q 1 bar are and for that we need to actually compute J 2 and K 2 right. So, actually we need some more space. So, what we will do is let me write Q 1 and Q 2 here in this small space. So, I am going to write Q 1 here Q 1 previous and Q 2 previous here. So, Q 1 previous and Q 2 previous to begin with was 0 and 0. So, what is J 2 and now we need this is a very important point we need to look at things just before this is active edge right. So, these are our active edges. So, we need to look at J 2 and K 2 and J 1 and K 1 as well just before this active edge. So, that means what was the situation at J 2 and K 2 just before the active edge J 2 was getting Q 1 bar which was Q 1 was 0. So, therefore, Q 1 bar must have been 1 that is 1 and K 2 was getting Q 1 which was 0. Now, this tells us that Q 2 the next Q 2 would be 1 right. So, now next and Q 1 of course, we know that we will just keep toggling every time. So, this as become 1 and 0 and 1 and 0 this table this column of the table we can fill up even without any reference to Q 2 and that we that is we already done in here done over here in the plot. So, now what is the situation this 1 1 will actually come here this become the previous values now and now we are at this point right. Now, we are looking at. So, Q 2 as become 1 and now we are looking at just before this edge that means Q 1 is 1 and Q 2 is 1 that is what is in this table here. So, what is J 2 J 2 is the same as Q 1 bar which is 0 and Q K 2 is the same as Q 1 which is 1 and therefore, this is going to reset the flip flow. So, this is going to reset the flip flow and you can complete one more cycle and so on. So, now this 0 this 0 0 will come here that these become the previous values now right J 2 will now become the bar of this and K 2 will become 0. So, therefore, the next Q 2 will be 1 and so on. So, it actually in this particular example it turns out that Q 1 and Q 2 are identical they are just they are both following the same pattern all right, but so the point here is not what the circuit is doing, but how to go about drawing these waveforms and this kind of table is very very important without a table without a systematic approach you really one can really easily get lost. So, it is better to write down this table and then complete the waveforms all right. So, I think that is probably the last slide of this presentation yeah. So, that is what is being shown in this table here ok. So, the final comment is that note that this circuit is not really doing much as we have seen because Q 1 and Q 2 are identical it is not doing much apart from taxing over mine, but hold on some useful circuits will appear soon and that is what we will do in the next presentation. Let me go to the next presentation and then we will look at we will start looking at counters and such ok. So, let us just continue with J K 3 flops and now before we actually come to some counter counters it is important to point out more inputs that J K 3 flop can have and those are the set direct reset direct and set direct input these are called these are called asynchronous inputs and why are they called asynchronous inputs because they have nothing to do with the clock they can override the clock right. So, if for example, set is 0 the set is 1 then that does not matter what all other inputs are. So, if S is 0 R is 1 it does not matter what these others are and Q n plus 1 becomes is forced to be 0. If S t is 1 the set direct input is 1 reset input is 0 then it does not matter what these are and the flip flop is set to 1 1 1 of course is invalid because then it is ambiguous and if both of these are 0 then the normal flip flop operation continues and that is what we have been assuming in the last in the last presentation. We have assumed that this flip flop is active that means the set and reset direct inputs have been made in active. So, then of course, if there is a positive edge ticket flip flop then we show an edge here and then the normal J K flip flop table that is called normal operation alright. So, a few points about this slide clock flip flops are also provided with asynchronous or direct set and direct reset input S D R D they actually they are called by different names sometimes it is called preset and clear which override all other inputs J K and clock. Now, these inputs in some chips they can be active high in some other chips they can be active low. So, if it is a if they if they are active low then they are denoted by not S D and R D, but S D bar and R D bar. The asynchronous inputs are convenient for starting up a circuit in a known state when you turn the circuit on a complex digital circuit on you can force this all these flip flops into specific state by using these asynchronous inputs otherwise your whole digital system will be in some kind of an uncertain state which of course, we do not want alright. So, there is then the D flip flop which is a special case of a J K flip flop with K and J and K being inverse of each other and again that can come in two varieties positive clock positive edge triggered D flip flop or negative edge triggered D flip flop. And so, you can actually look up the draw the J K flip flop table at this point and show that if this connection is made then only J equal to 1 K equal to 0 or J equal to 1 N T those are relevant and that corresponds to this table. If D is 0 then Q N plus 1 is supposed to be 0 if D is 1 Q N plus 1 is supposed to be 1. So, what is the D flip flop doing? It is actually essentially causing a delay of 1 clock pulse between the input and output. For example, in this case the input is like this and the output this will appear at output one cycle later and that is because as we have been repeatedly stressing we need to look at things just prior to the activate. So, just prior to this activate D is 1. So, therefore, just after the activate D will become 1 here. So, therefore, in other words it will introduce a delay of 1 clock cycle. There is a shift resistor now again this the font size may be a little small for you but, let us just look at the waveforms you might be able to see those. So, there is a shift resistor in which there are 4 D flip flop with inputs D 1 D 2 D 3 D 4 and output Q 1 Q 2 Q 3 Q 4. There is a clock given and the input at the first D input is given. So, that is what this looks like and now we are asked to plot Q Q 1 Q 2 Q 3 and Q 4. So, you can actually work out such a problem in class. So, that the students get a feel for what a D flip flop does and this can be done one at a time because this D is going to act as an input to this flip flop and that alone is going to determine what happens to Q 1. This Q 1 is going to act as an input to this second flip flop and that alone is going to determine what Q 2 looks like and so on. So, therefore, you can do this one at a time. So, Q 1 the moment D is given Q 1 is known. The difference between the input and the output here is that this output Q 1 gets sort of synced with the active edge of the clock which is which in this case is which in this case is negative. So, the active edge here is negative and therefore, it is getting synced with Q 1 has got synced with the active edge here. Next we have Q 2 and Q 2 is a delayed version of Q 3 and so on. So, essentially the data is just shifting. So, Q 4 is a delayed version of Q 3 which is a delayed version of Q 2 and so on. Now, this can be actually represented in a little transition diagram like that and it may be a little the font size again may be a problem for you, but just look at it later and it is convenient to show in class if you want to. This shows the moments of the data how that goes through the various stages and we can try to explain this figure in class. There is something called parallel transfer between shift registers and you often need to do that if there is if you are doing some operation in which there is a shift register involved that shift register you want to load initially with some data. So, that is where this is important. So, there is a register A here the top one and there is a register B the bottom and what we want to do is there is some data in A already and that data we want to shift they want we want to transfer to the B register. So, that can be done by connecting this output of the first flip flop here to the input of the first flip flop here and so on. The second flip flop the output goes to the input of the second flip flop here and so on. So, now what will happen is one clock edge the active edge will essentially make this transfer make this top data transfer to the bottom data that is called parallel transfer between shift registers. You can also explain what a bi-directional shift register is and it is with some simple logic you can actually achieve this job. So, what is doing here what is done here is there is a D R and input data data right that means this is going to shift right there is a mode input and there is a D L or data left this is going to shift left and it is sort of simple easy to see how this works. If mode is one then this top gates are actually activated and this mode bar is going to the bottom gates the bottom and gate. So, if mode is one only the top gate is sort of passing these values and the bottom gates are just putting up putting out 0. So, if mode is one this input is 0 here this input is 0 here and so on and the data then will this D R will come here and this output of this one then will come here and so on. If mode is 0 then mode bar is one and then the bottom gates now are active and then this D L is now connected to the last flip flop here the output of this flip flop is connected to the input of this flip flop and so on. So, now you see that this the data will prove in that direction. So, we will take a look at take a more detail look at this later and you will figure out this pretty easy to understand this circuit. So, that is called a bi-directional shift register. There is a very very interesting application of shift registers and that is multiplication using shift and add. Now, this is of course a little too small for you to see perhaps, but you can take this example and explain how multiplication can be done by doing simply shift and add. So, this on the right we actually show that procedure in detail. So, maybe you can see at least this part. So, we are we are essentially multiplying two numbers 1 is 1 0 1 1 binary that is decimal 11 the other one is 1 1 0 1 that is 13 and how do we do this first we load this top number here 1 0 1 1 and that is being done here that is loaded the first number is loaded here 1 0 1 1 then what we do is we look at we load this second one with 0s and that those are these 0s and now since b 1 is 0 if b 1 is sorry since I think this in this table the one step is kept. So, just look at this part and then you can actually correlate the left and the right and so what is happening is here we are we are taking this the contents of the first register shifting it left then doing an add then the contents of the register we are again shifting left whenever you shift left you are padding these things with the 0s those are these red here and then finally, when all of these after 4 clock cycles you will get your result. So, that is what is shown in this table here the step by step procedure and in fact, there is a there is a very useful very interesting hardware experiment that you can set up with this. So, you can ask the students to multiply 2 4 bit numbers using this process it is a fairly involved circuit, but it can be done in about 3 hours time. So, you can set up an experiment based on this is nothing, but what we do in decimal numbers as well we take one of these numbers one at a time then we pad it pad that with 0s we go on adding and so on is the same thing in binary as well. So, we will take a look at this example in more detail later now parallel in serial out data moment. So, sometimes what we want to do is there is there is some data that we want to load into a shift register and then we want to shift it either right or left. So, that is what is shown here. So, there is a clear pulse the clear pulse will essentially clear if that clear line is going to all of the reset input that will just clear all the flip-flops then there is a load pulse that load pulse is going to these gates here. So, what that will do is if your a 3 for example was 1 then it will load this flip-flops with 1 if a 2 was 1 it will load that with 1 otherwise with 0 and so on. So, this after the load pulse this flip-flops will actually have the data that is applied here to these and gates. So, that data will come here and now we want to shift it. So, then after that both the clear and load inputs are inactive that means this ST and RD the set direct and reset direct are now inactive and therefore the normal operation of the flip-flops will continue and the flip-flops will start seeing the clock and so on. So, then the clock is shown over here and as a result of this clock then this normal shift register will work and this actually is shown here in pictorial form. So, let us say this is our data. So, this circles could be either 1 or 0 now step number 1 is to load this data. So, that is what that does step number then after that after every clock pulse this data will keep getting shifted and finally of course since this input is connected to 0 all this 0 will essentially come to all of these flip-flops.