 Hello, and welcome to this presentation on power MOSFET technology switching behavior in motor control applications. In this presentation, we will learn the typical EMI-EMC behavior in the major low-voltage motor control topologies, in particular three-phase inverter and half-bridge topologies. This presentation discusses the effect of certain MOSFET-K parameters, especially in the transition phases, where the MOSFET switching directly influences the radiated and conducted electromagnetic emissions on the most common motor control topologies. The figure shows the drain currents of two devices of the same leg when turning on the high side, HS power device. First, the turn-on phase, section number one, with current directions and their flowing path are shown in the figure. When switching on the HS device, section number two, the current on this leg has some oscillations, which are also reflected on the low-side LS device due to the recirculation current in the freewheeling diode. At this stage, the phase current will not change direction. Once the device is finally switched on, section number three, the current on the LS has already completed the freewheeling stage, while the HS current grows to the maximum loading value. The recirculation current significantly impacts the system's efficiency and emissions. The figure shows the turn-off and turn-on phases of the power device placed on the high side of the three-phase bridge. In this case, the three system currents were simultaneously monitored. On top of that, the phase motor current, I out, is also considered. Phase one, the high-side MOSFET is turned on and the current is positive and increasing. No current flows on the low side while the phase current of the motor follows the trend of the high-side current, also flowing to close the loop through the low-side device on the other leg of the bridge. Phase two, the high-side device starts to switch off and then the current through it goes to zero. As I out cannot be suddenly reduced to zero and cannot change direction, it will find a freewheeling path through the body-drain diode at the beginning and then in the channel of the same leg of the low-side MOSFET. Phase three, the high-side device is again turned on. The current reaches a peak due to the LS freewheeling current and then flows on the high-side. The I out current starts to increase again. The figure shows a classic schematic diagram of a tri-phase inverter of a brushless DC BLDC motor, as well as the measurement equipment used to evaluate the system's efficiency. The input and the output power can be calculated by using two different insertions, a volt-amperometric insertion for the input power and an aeron insertion for the output power, useful in balanced system loads. The efficiency will be the ratio between the two measured power values. The figures show the typical behavior when turning a MOSFET device off and on in a three-phase bridge topology as previously shown. The VDS drain source, the VGS gate source voltages of the low-side device as well as the current flowing through the device under analysis with the positive direction from drain to source are shown. The losses can be calculated during a single switching transient. The VDS and IDS crossing phases are considered in order to evaluate the device's losses and their impact on the system's efficiency or for a specific benchmark or comparison between different devices or technologies. The maximum switching power consumption at the device turn-on-off or evaluated shows the three most important parameters that have an impact on the power losses and, as a consequence, on the device's temperature as a result of its heating up. The on-state resistance, RON, has an impact during the conduction phase. The gate charge, QG, during the switching and the reverse recovery charge, QRR, during the diode recovery phase. The figure on the right shows a comparison obtained using the previous circuit between the STL285N4F7AG MOSFET and a competitor's device. Although it has a worse on-state resistance, RON, the STRIPFETF7 device shows a lower case temperature thanks to its lower switching losses that compensate for the conduction ones. The slide shows a very stressful condition that happens when the rotor is locked. The competitor device shows a higher reverse recovery current, IRRM peak, as well as a greater recovery charge, QRR, and recovery time, TRR. The STL285N4F7AG, even with a higher RDS on, is much more suitable than the competitor MOSFET for BLDC motor control applications thanks to its better dynamic parameters. It shows faster rising and falling times and a lower reverse recovery charge, QRR, better matching the specific requirements of motor control applications. The STL285N4F7AG reaches full turn-on in about 2.5 microseconds, while the competitor device reaches the same voltage in almost 3 microseconds. In general, the turn-on off times depend on the device and on the driving network. Higher times lead to higher losses but lower emission values during switching. Due to the slower switching to make similar the transition phase of the two MOSFETs, the gate driving resistor for the competitor device was reduced. The voltage oscillation phenomena seen in the previous slides during the HS turn-on can also be observed in this circuit topology. The oscillations occur at the beginning of the miller plateau, depending on the non-optimized capacitive ratio and on the miller effect. The figures show the gate source voltages, VGS, of the four devices of the H bridge during the switching phases. The turn-on and turn-off phases are affected by both noise and oscillations. The zoom during the oscillations shows that the frequency of such oscillation is around 277 MHz and match the bandwidth where the highest EMI emission rate is registered as shown in the right side of the figure. The voltage oscillations are generally induced by power MOSFET intrinsic capacitances, whose values depend on VDS, miller effect on MOSFET, and parasitic capacitances inductances of schematic tracks in the PCB layout. The figures show the turn-on and turn-off phases of the same devices after some circuit modifications. The voltage ringing disappeared and the controller is working properly. Such a condition was obtained by the following modifications. Replace the RG-off resistance of device 2 LS with a shortcut. Therefore, this gate resistance, RG, is set at zero ohm, reducing the CGS capacitance of device 2 LS from 10 to 2 nanofarad. Remove the CGS capacitance of device 4 HS, open circuit, and the snubber fine tuning. The figure on the right side shows the radiated emissions measurements after these modifications. The only residual peaks are probably due to the controller's power supply. The modifications can minimize the effects, but they can also slow down the device or increase its switching losses. It is always better to use a device with better intrinsic characteristics in terms of body drain diode and capacitive ratio, CRSS-CISS. The figure shows the typical current path during the device turn-off phase. The board was upgraded to minimize the miller effect. Minimizing the RG-off resistance and inserting the 2 nanofarad gate source capacitance in the low side reduces the gate-to-drain and gate-to-source charge ratio by one more step. A lower CGD and higher CGS will reduce the residual VGS, capacitive divider, when the device is off. Considering the VGS bouncing, the total gate resistance multiplied by the gate to drain capacitance and the voltage variation dV dt, where RG-TOT is the sum of the intrinsic RG, plus the external gate resistor, RG-off, plus the output driver resistance, RDRV. If the VGS is next to or above the FET, the VTH may produce a sub-threshold conduction of the FET that is the root cause of the noise and, in the worst case, may result in cross-conduction in the half-bridge, destroying the complete system. Therefore, fine-tuning the gate-source capacitive ratio, if externally forced by the circuit setup, and reducing the RG-off can minimize the spurious bouncing on the gate-source voltage. The layout has an impact on the behavior of the various bridges because the PCB tracks have stray inductances that affect the DIDT, and therefore the oscillation as well, RCL Resonant Tank Circuit. Modifying the RG-EXT and the IC driver next to the gate pin can improve the FET's switching. This means L-stray minimization and effective smoothing of oscillations that generate EMI emissions. A board's layout can be critical in terms of track lengths and widths, circuit areas, and the correct routing of the traces. To better drive the MOSFETs, the signal tracks such as the one for driving the gate of the devices must not be surrounded by the ground power track. The parasitic inductances due to PCB traces could have an impact on the EMI issues and on the overvoltage spikes. Another factor that influences the current and output voltage spike behavior during the turn-on and turn-off phases of the devices is their output impedance consisting of C-OSS and R-OSS. The higher the impedance, the higher the ability to dampen the oscillations. The figures show the turn-off phase of two 100 volt devices with different technological characteristics. The voltage and the current ringing of device 2 is lower than the other one thanks to the output resistance characteristics. Device 2 has an output resistance higher than device 1 which also has a less stable pattern compared to it. This instability leads to greater voltage ringing during shutdown. The output capacitance should be a trade-off between a low value to minimize the switching losses and a high one to avoid first spikes and the following oscillations that produce EMI issues. The freewheeling diode softness as already explained plays a fundamental role on the power system emissions and efficiency. The low side device should have soft switching without dangerous voltage spikes and high ringing frequencies between the drain and the source. This behavior can be achieved by using a power MOSFET with a low reverse recovery charge, QRR, that has a direct impact on the VDS overshoot. A higher QRR means higher overshoots due to the extra current in the stray inductances. A lower VDS overshoot and ringing reduce the potential risk of a latch-up failure event or dynamic DV-DT failure issue. An improvement in terms of emissions was achieved by using the StripFET F7 trench gate technology which significantly reduces emission rates in applications. The above figure compares the MOSFET current on the freewheeling diode, the old planar technology and the standard trench gate structure with the most recent advanced StripFET F7 trench gate technology. The traditional trench gate structure improves the QRR, which reduces power losses during the turn-on phase thanks to a less deep recovery peak current. The advanced trench gate technology is an improvement of the previous one with the same IRRM but with an improved diode softness. The energy loss during turn-on phase will be lower due to the high circulation current and its oscillations are smoothed. This produces smoothed switching without any hard oscillations as well as improved EMI sensitivity. In addition to setting a single Miller transfer cap to reduce EMI sensitivity, another important parameter is the CRSS-CISS ratio with maximum amplitude at VDS equals zero volts and its smoothed decreasing trend at a higher VDS. The left figure compares trench technology devices also versus the old ST planar tech with main competition suppliers. This ratio is a good indicator of how the StripFET F7 technology controls the DIDT and DVDT during the transient phases. The right figure shows the trend of the reverse transfer capacitance of two devices belonging to different technologies. The planar technology device shows a hard drop of the capacity variation versus the voltage, while the StripFET F7 trench gate structure has a smoothed one. The figure compares conducted emissions between an ST device, green, and competitor devices using an Agilent E7402A EMI test receiver with a line impedance stabilization network, LISN, between 150 kHz and 100 MHz. Also, for these kinds of emissions, the device with a better capacitive ratio and diode softness shows a lower conducted emission, green wave form. Comparison is performed with two different competitors. The figure shows the radiated emission of two different ST devices, same size and voltage in trench and planar technologies in a tri-phase inverter application. At the same loading conditions, the two devices provide different results. The trench one has less and lower emission peaks than the planar one over the whole frequency range monitored during the analysis. This good result is mainly due to a lower QRR and excellent softness of the body drain diode and to a correct capacitive ratio of the StripFET F7 technology. The StripFET F7 MOSFET is a perfect device for protecting system sensitive to EMI-EMC issues, especially in motor control applications, thanks to its body drain diode with low recovery charge, QRR, good softness and correct CRSS-CISS ratio. The constant ESR of COSS quickly smooths the voltage oscillation, too. For further information about low voltage power MOSFET switching behavior and performance evaluation in motor control application topologies, please refer to our dedicated application note, AN5252, available on www.st.com.