 Hello everyone, my name is Ms. Shweta Yaspatil, working as an assistant professor in the Electronic and Telecommunication Engineering Department at Varchan Institute of Technology, Solaapur. Today's topic is the Demultiplexer and Decoder. Learning outcomes. At the end of the session, the learners will be able to design a demultiplexer circuit, design a decoder circuit. Contents. First is the general block diagram of demultiplexer. Example of that 1 to 2 demultiplexer. General block diagram of decoder. Example of that 2 to 4 decoder. Difference between demultiplexer and decoder. First recall, what is multiplexer? It performs many to one operation. Demultiplexer. A demultiplexer works in opposite to a multiplexer. It performs one to many operation. This is the general block diagram of demultiplexer. It has one input and two raise to n outputs, where n is the number of select lines. So, it is also called as one to two raise to n demux. It is sometimes called as data distributor. Because one input data acting as a source and several outputs are acting as a destination, only one input data is distributed to only one of the several output. So, it is called as data distributor. It transmits input data to one of the output which is controlled by n select lines. This is the symbol or block diagram of one to two demultiplexer. Input data A which can be connected to Y or Z according to select line one at a time. This is the truth table for the one to two demultiplexer. When select line is equal to zero, Y is equal to A. When select line is equal to one, Z is equal to A. But A may be zero or one, so that there are four possible combinations in the truth table. When select is equal to zero, Y is equal to A as it is. At that time, Z is equal to zero. When select is equal to one, the Z is equal to A as it is. At that time, Y is equal to zero. K-map and Boolean expression. This is the K-map for Y output. In the truth table, Y output is one when select is equal to zero and A is equal to one. So, here when select is equal to zero and A is equal to one, in the square of this K-map one is entered. So, we get Y is equal to select one dot A as a Boolean expression. This is the K-map for Z output. In the truth table, when select is equal to one and A is equal to one, Z is equal to one. So, this output one is entered in the square when select is equal to one and A is equal to one. So, we get the expression for the Z is equal to select dot A. The logic gate diagram. When input data A is equal to one and select is the zero, at that time first input AND gate will be enabled. So, Y is equal to one. When A is equal to one and select is equal to one, second AND gate will be enabled which produces output high Z is equal to one. This is the timing waveform for the one to two D multiplexer. Here A and select line are the inputs, Y and Z are the outputs. A input is the clock pulse with the less time period and select is the clock pulse with the maximum time period. Y is equal to A when select is equal to zero, Y is equal to zero otherwise. When select is equal to one, Z is equal to A and Z is equal to zero otherwise. Decoder. This is the general block diagram of decoder. A decoder is a circuit that has N inputs and 2 raise to N outputs where N is equal to 2, 3, 4, etc. N to 2 raise to N decoder provided with the enable input so as to activate the output based on the data input. Decoder converts encoded signal back to its original form. Since there are 2 raise to N outputs, there will be only one output asserted at a given time. There are 2 types of decoder, active high output type decoder and second is the active low output type decoder. This is the symbol or block diagram of 2 to 4 decoder. Here A and B are the 2 inputs given to this decoder. F0, F1, F2, F3 are the outputs of the decoder. It is one hot decoder because output is active high according to the input given. This is the truth table for the 2 to 4 decoder. When input code is 00, F0 is active high. When input code is 01, F1 is active high. When input code is 10, that is in decimal 2, then F2 is active high. When input code is 11, that is in decimal 3, at that time F3 is active high. Boolean function, F0 is equal to summation of A, B of 0th combination. This 0th combination is equal to A bar dot B bar. This is obtained from the truth table. F1 is equal to summation of A, B of 1st combination A bar dot B. F2 is equal to summation of A, B of 2nd combination A dot B bar. F3 is equal to summation of A, B of 3rd combination A dot B. This is the logic gate diagram for the 2 to 4 decoder. 1st AND gate will be enabled which produces F0 is equal to 1 when input A is equal to 0 and B is equal to 0. When input A is equal to 0 and B is equal to 1, 2nd AND gate will be enabled so that F1 is active high. When input A is equal to 1 and B is equal to 0, 3rd AND gate will be enabled which produces F2 is equal to 1. When A is equal to 1 and B is equal to 1, 4th AND gate will be enabled which produces F3 is equal to high. This is the timing waveform for 2 to 4 decoder. Here input code 0011 is given and B as a 0101 input code is given. F0 will be active high when 00 input code is present at the input of the 2 to 4 decoder. F1 is going to be active high when at the input 01 code is present. When input code is 10, F2 is active high, other times it is 0. When input code is 11, F3 is active high. This is the difference between demultiplexer and decoder. Demultiplexer is the inverse function of multiplexer. Decoder is the inverse function of encoder. In demultiplexer, output line is determined by select line. In the decoder, it has no selection lines. Demultiplexer transmits data from one line to two raise to yarn possible output lines where the output line is determined by yarn select lines. Decoder takes yarn input lines, produces two raise to yarn output lines which is exactly opposite of what an encoder does. Demultiplexer is a combination circuit that is used to implement general purpose logic. It routes a single input signal to one of many output signal. Decoder is a logic circuit that decodes an encrypted input stream from one format to another. Demultiplexer classified as 1 to 4 demultiplexer, 1 to 8 demultiplexer and 1 to 16 demultiplexer. And decoder is classified into 2 to 4 decoder, 3 to 8 decoder and 4 to 16 decoder. Demultiplexer are used in communication systems and networking solutions for security purposes. And decoder used in many applications such as data demultiplexing, memory address decoding, etc. These are the references.