 Hello, and welcome to this presentation of the STM32L4 power efficiency optimization with an external SMPS. The use of an external switched mode power supply, or SMPS, with the STM32L4 series of ultra-low power microcontrollers extends the power efficiency in run modes. By generating a V-core logic supply from an external DC to DC converter instead of the integrated LDO regulator. For example, it allows a power consumption gain up to 60% at VDD equals 3.3 volts. This feature is supported by devices marked with a trailing P-suffix, where two GPIO pins are replaced by a VDD12 logic supply connected to the external SMPS. A wide range of external SMPS can be accommodated with the use of an external or built-in switch. For proper operating mode, the VDD12 power supply rules must be respected. Here is a typical implementation of an external SMPS for an STL32L4 device with the use of two external components. The SMPS component, controlled by GPIOs if needed, and the switch component to isolate the VDD12 pins during low power modes or transition phases, such as power-up or asynchronous reset. The two GPIOs are chosen with the least impact in terms of functionalities and replaced by VDD12 pins. Please refer to the product data sheet for more details. Two embedded linear voltage regulators, the main and low power regulators, supply all the digital circuitries except for the standby circuitry and the backup domain. When V-core is provided by the main voltage regulator during run, sleep, and stop-zero modes, the VDD12 can be supplied by the external SMPS by closing the external switch. When V-core needs to be powered by the low power regulator during low power run, low power sleep, stop-one and stop-two modes, or switched off during standby and shutdown modes, VDD12 must absolutely previously be disconnected from the external SMPS by opening the external switch to avoid any destructive impact on the regulator. As the VDD12 voltage directly supplies the internal logic, the following rules should apply. VDD12 must never exceed 1.32 volts. VDD12 must be higher than 1.05 volts when sysclock frequency is below or equal to 26 MHz. VDD12 must be higher than 1.08 volts when sysclock frequency is above 26 MHz. During transition phase, such as power-up or asynchronous reset, the VDD12 pins must be disconnected from the external SMPS. Transitions from connected to disconnected configuration are only allowed when the sysclock frequency is below 26 MHz. The SMPS can only be connected to the device during run, sleep or stop-zero modes and when VDD12 is greater than the main regulator output voltage by 50 millivolts. In other power modes, the SMPS must be disconnected. Please have a look at the application note AN4978 for more information. This graph summarizes the power supply rules allowing safe transitions. After reset, the system clock frequency is 4 MHz and the main voltage regulator is in voltage range 1, supplying a V-core at 1.2 volts. If the SMPS supply voltage is greater than 1.25 volts, the SMPS can be connected and then the system frequency increases to reach maximum performance possible in this low power range. If the SMPS supply voltage is lower than 1.2 volts, switch the main regulator to voltage range 2 and then the SMPS can be connected. In this mode, the chip can run in high performance range when the SMPS voltage is greater than 1.08 volts. The expected power gain with the external SMPS is directly linked to the power efficiency of the regulator. The STM32L4 microcontroller embeds low dropout regulators whose power efficiency is given by the ratio of the output voltage to the input voltage. When the output voltage is close to the input, the power efficiency is good, but can get worse as soon as the input voltage increases. On the contrary, the SMPS power efficiency remains almost constant whatever the voltage input ratio, generally between 80 and 95% depending on its input voltage and current load. We can compute the expected power gain with the provided formula. See AN4978 for more details. As an example, the Nucleo SMPS board has a gain of around 60% at input voltage 3.3 volts. Here is an example of the power consumption graph of a core mark at 80 MHz as a function of the VDD supply using an STM32L496ZG microcontroller on a Nucleo 144 SMPS board. We can clearly see the power gain increasing with the voltage. For more details, please refer to the application note design recommendations for STM32L4 with external SMPS. Please also refer to the product data sheet for the available packages supporting the external SMPS feature.