 Hello everyone, welcome to lecture on test bench for multiplexer. At the end of this session, students will be able to build the test bench for multiplexer and also able to verify the VHDL module design for multiplexer with the help of this test bench. Now, before starting with the actual session, let's pause the video and think about what is a multiplexer. If you remember, in the previous video lecture series, we have covered the different VHDL design module for multiplexer, demultiplexer, half adder, full adder, encoder, decoder, comparator, right. So, if you saw that videos previously, then you know that what is a multiplexer. So, multiplexer is nothing but which has multiple inputs and one output, means it is having multiple inputs. Now, in this case, it shown over here it has to one multiplexer, eight inputs are there and one output is there, right and from these eight inputs, any one is selected and connected to the output with the help of these three selects line. So, number of these selects line depends on the number of inputs, that is a 2 raise to n, 2 raise to n equals to m, m equals to nothing but your inputs, n is nothing but the number of lines, select lines. So, 2 raise to 3 equals to 8, so to satisfy that eight inputs, three select lines supposed to be there. So, this is how you can find that how many select lines supposed to be there for that particular multiplexer, right. So, now before writing to the test bench for any design, you must know the VHDL module for that, right. So, to write before writing the test bench for a test to one MUX, let us have a look at the VHDL module whatever we design in a previous video lectures, right. So, we know that for every VHDL module, we have three important part, one is a library declaration, second one is entity and third one is architecture. So, we have to include the libraries first, so library included from that which package you are using that package is mentioned over here, right. After that we have to declare the entity, so here entity, entity name is there is then you have to write the port declaration in the entity, port which contains the inputs and output signals are there. So, inputs here I have taken as a bit wise, you can take as a vector as per your choice whatever you feel the convenient way, right. Then S is a taken as a vector which is a select line, three bits, so two down to zero and Z is the output single bit, single line, so type of bit, right, then end entity. Once you done with that input and output declaration of your device or system for which you are writing the VHDL module, you have to end the entity, next part is a third part of your VHDL module is a architecture, right. So, architecture, architecture name supposed to be there of for which entity you are writing the architecture that entity name supposed to be there, so same name is here MUXET, here also MUXET is then architecture begin, after that your architecture starts, that is architecture is what which gives you the functionality or description how your circuit is or how your it is to one MUX is going to behave, right. So, for that we have written in the process, process inside the process bracket you can see that there are sensitivity list which affects your output, right, so sensitivity list is nothing but your signals which are affects the output I0, I1, all the input signal and select line is there, if is there any other signal also there and that affects the output in that case also you have to mention that one. Then your process begin, now in the process we have written all the cases with the help of case statement, case S, when case S, S is select line, when select line having a combination because of three bit in a select line, eight combinations are there, when the combination is 0, 0, 0, 3, 0, in that case your Z is connected with the, Z is assigned with the value of I0, I0 means your one input line, I0 input is connected to Z, when S is having combination 1, 0, 0, 1, in that case Z is assigned with the value I1 input, whatever the input I were having that value assigned to Z, so this is how you can write for all the combinations of your S signal, once you done and if you are S having value which is not a part of this combination, in that case you are assigning Z with the 0, that is we have written that is a optional field, if you want you can write that, otherwise you can make it Z assigned with the value Z instead of 0 or you can make it as 1 as per your requirement, once you done with all the cases you have to end the case statement, so end case, then you have to end the process, so end process and then you have to end the architecture, so end architecture name, so this is the VHDL module for 8S to 1MUX multiplexer, you can use the simulator, there are different simulator tools available in the market, you can use anyone, there are different software also, use anyone to write the VHDL code, use the simulator tool and perform the simulation and you can verify whether your code is working properly or not with the help of observing the waveform, same I used one simulator called ICIM and I perform the simulation and this will show the output like this, so these are the inputs I0, I1, I2, I2, I7 over here, then select lines are there, this is the select line of 3 bits, so that is why it is showing like a bus, these are the individual bits single line, then according that whatever the value of this S having, according that the input is selected, now in this case now the value is 0, 0 means first I0 input is selected, so that is why during this period the value of I0 is 0, so that is why output is 0, after this period the value of I0 becomes 1 and the select line having still 0, 0, 0, so that is why output become 1 over during this, now after this the select line became 0, 0, 1, though my I0 input is 1, but the select line is having value 0, 0, 1 means my I1 signal is input connected, so that is why output become 0 again, so this is how you can verify the simulation for 8S to 1 multiplexer, now let us go for the test bench writing for this 8S to 1 multiplexer, for the test bench writing again the same way you have to write that library declaration supposed to be there, entity writing supposed to be there, architecture is supposed to be there, so first library declaration part, then entity declaration, but here the entity is supposed to be empty, nothing to write in that entity just mention the entity keyword entity name, then end the entity that is it, once you done with the entity declaration go for the architecture writing, architecture name of for which entity you are writing architecture we are writing for this, so this name is supposed to be there is, then component declaration over here, now component declaration is what we are using whatever the previously created VHDL module that entity as a component, so we are using the previously created entity as a component, so that is why it is mentioned as a component, same power declaration going to be there as you done in a entity part in previously created VHDL module, so I0, I1, I2 you can write in comma format or you can whatever the you have taken input type during the entity creation same supposed to be there, I have taken previously as a all the individual see input signal type bit, so that is why I created like this, then S is a input again select line that is type of bit vector 2 down to 0, Z is output, once you done with the component declaration end the component, then comes the inputs and output declaration which are going to be mapped with the signals of your component, so how much inputs and outputs are there that much you have to declare signals, so signal I0 get taken and values assign initially some value, similarly remaining signals then output is also taken, see the for input assign the values initially output according that input output value is going to be changed, so that is why output is not assigned with the any value, once you done with the signal declaration part you have to write the constant here, this one is optional you can use that or you can go directly for the 110 nanosecond whenever there is a period you are using in a next code, after that your architecture begin actual architecture, so whatever the code you have written between the architecture line and this begin keyword all are the declarative part remember, then you have to write the component instantiation whatever we created a component previously, so format for that or syntax for component instantiation we already know that we have to write the label first then component name then port map and then the bracket you have to map the signals, position and mapping is that, so I0 is mapped with I0, I1 is mapped according that the mapping is done, S is mapped with S and output is mapped with the output, once you done with the component instantiation we have to write the process now right, so process then process begin right, now here we are writing all the cases, so first case S having value 3 bits all 0, in that case what will be the output, so how to write that, so S assigned with the all 3 is 0s, we have waited for period, so we have taken period as a constant and time assigned to that is which of type time value assigned to that is 10 nanoseconds, so instead of this you can directly write wait for 10 nanoseconds right, then after that we have used assert statement, assert statement is used to check the Boolean condition right and if that condition fails I am saying fails then and then it generates the report statement, if that condition true it will go for the next case right, it is opposite functionality is opposite to your if statement, if statement how works whenever the condition true it comes in a loop, here whenever the condition fails it comes in a loop, so if assert statement checks the Boolean condition if that fails it generates the report statement, otherwise it will not generate this report statement right, so remember this one, so for this one S assigned with the value all 0, we have waited for 10 nanosecond period and then we have asserted check that Z equals to I 0, if Z equals to having the value which is on the I 0 input line then that is true it go for the next case, if that is not true that fails it generates the report statement, now here it is a text message displayed that is test fill, you can use anything and the report statements of various type, it can be note type, it can be warning type, it can be error type, so this one is a error type, severity error and message displayed like this right, this is one case of your S that is select line, you have to complete write the all other cases right, all other cases means three in three bits are there for a select line, eight cases are there right, so we have to complete all the cases, after writing all the cases we have to end the process, so end process right, then you have to end the architecture, so end architecture, so for short form I have just shown one case you have to complete write all the cases right and then once you done with the code writing for test bench, you can use the same software whatever you used for creating the BH0 module and you can use the same simulator and if you perform the simulation it will show you the output like this right, the same I used, so these are the inputs one is having I 0 is having value 0, I 1 is having value 1 that is why it is filled with the green color right, I 2 is having 0 again, so that is why it is having 0, I 3 is having 1 again, so it is filled with, so I alternately kept value 0 1 0 1 0, so that is why it is showing like this and then the Z S line, S line is having combination all I have kept here 0 0 whatever the combination we tested while writing the test bench, all combinations are there and according that I am getting the output over here for 0 0 0, your output is selected line is I 0, I 0 is having 0, so that is why output is 0, for 0 0 1 select like output Z is connected with the I 1, I 1 is having value 1, so that is why output I 1, so this is how you can verify your test bench also with the help of simulation right and simultaneously you can verify your VHDL module, whether your VHDL module is working properly or not with the help of this test bench right, so these are the references, thank you.