 Welcome to the lecture series on VLSI advanced VLSI design course. Today, I will discuss about basics of VLSI test. During last lecture, we discussed about the test economics, why test is so important, how much it will cost if you apply a sequence of test vector onto your chip. And we discussed that it has two parts, one part is to generate the compact test set and then you have to apply that compact test set to each and every chip. And now when you apply test to each and every chip, it cost you something about 2 to 5 cents per second. That means, if you test your chip say for a minute, it may cost you about 5 dollars, sorry about 3 dollars and hence it is too expensive to apply a test for minutes. Therefore, we have to test our chip somewhere between few seconds to minutes. That is the reason for time. But we have also seen that if you want to apply functional test, so that means if you want to apply all sequence of test vectors that may be applicable to a chip, say a chip has n inputs, then there are 2 raise to the power n inputs you can apply. And today's chip have say hundreds of inputs, then it may take billion centuries. Now, you see the difference between the exhaustive test and reasonable time in which you can apply the test. So, there is a huge difference. Now, it is the responsibility of test engineers to bring down this exhaustive test to a test set which is available to a chip. This is which can be applied in reasonable time and it gives you almost similar confidence that you would have got from the exhaustive test. So, now here let us look at what are the various methodologies, how I can generate that compact test set that can be applied within few seconds. As I discussed earlier as well that how good your test set should be that depends on how much defect level that you can afford to. Like for example, for automotive applications, the kind of defective parts per million manufactured parts they are looking for are very, very low. Ideally, they want 0, but here that can be from somewhere from 1 to 10 defective parts per million manufactured parts are affordable. So, your test quality depends on what kind of DPPM figures you are looking at. Now, let us look at the test application process. So, you develop a compact test set that compact test set is stored on an automatic test equipment which is pretty expensive device. You apply that to your device under test, collect the test response and then bring back to the automatic test equipment. Automatic test equipment also stores the correct response of the chip and then it compare with the with the collected response. If there is a match the device is good, if there is a mismatch device is bad and then you have to throw that device out. So, this is the basic test methodology. Now, as I said that we will discuss in this lecture how we can generate this compact test set that can be applied in reasonable time. So, now look at what we want. Say I have a circuit under test, this circuit under test has say n inputs x 1 to x n. So, now here if I apply the input x 1 to x n the output say it has assume it as single output then it will evaluate as this function as f of x 1 x 2 x n when there is no fault. So, if say there is a fault or say there is a defect due to that defect the function may not evaluate same as this f. So, say this evaluates under the defective condition when I apply same input say x 1 x 2 x n the function will evaluate to f alpha. So, now the question is if this function which is defect free and the evaluation of function which is defective if both are same in that case here this input set cannot detect the defect, but if both of these are different in that case you can detect that device has defect. So, now our aim is to find out a set of or a sequence a input sequence that can detect all the defects which may possible in the device circuit under test. So, now and here the size of the sequence should be as small as possible and keep in mind we want to detect all the defect. Here I am using a word fault I will explain little bit later why we use word fault. So, for a while you can think of that fault and defects are synonym of each other, but keep in mind that we have interest only knowing whether a device under test is faulty or defective or it is defect free. We are not interested in diagnosing that what kind of defect or what kind of fault it has. So, it is like here go no go test. So, it will tell us whether the device is defective or device is defect free. So, as I said that I we want to develop a test sequence that can detect all the defect and one of the prime requirement is input x1 to xn can be the test for a given defect or given fault if it produces different output when there is a fault and without fault. So, that means here the function should be evaluated in different way that is the mandatory requirement. Now, if you look at if I have a circuit with three inputs in order to test that exhaustively what I need I exhaustively apply all the possible inputs and check whether I am getting the correct output which I am supposed to get. But here as we discussed earlier that this exhaustive test set is not applicable hence here. So, since we cannot apply exhaustive test set our best bet is to target the likely faults or likely defects which may occur during your manufacturing process. So, this brings us to a point. So, now here if I say that here I have to target few likely faults or defects let us define the basic terminology. We use three different terms defect, force and error. Defects are the physical flaw in the device which we discussed earlier that what are the various reasons to get defect while you are manufacturing a circuit. Forks are the logical manifestation of these defects. So, that means here due to a defect line may look like permanently in the case of stuck to logic 0 or permanently stuck to logic 1. So, that means here the effect is such that you see the effect like one line is connected to either power line or ground line. And now here when there is a fault it causes incorrect logical operation and then you will get the different functional output. So, now in the presence of a fault you will get an erroneous output. So, here defect is physical phenomena, fault is logical manifestation. So now this is at the device level. If we look at little bit higher level of abstraction then we will see the fault. So, now here so that means if you want to generate or develop a very compact test set we have to go one level of abstraction higher and so that means here rather than targeting defect I should target faults. So, that means here we are modeling these defects in terms of their manifestation as logical faults. So, now here likely the defects depend on the circuit layout or process control and all these likely defects are very difficult to obtain. So, as I discussed then here we go one abstraction higher and model these physical defects as logical faults and that is known as fault model. So now here the question so what kind of fault model we can have? Let us say the very simple fault model that was conceived way back 3, 4, 5, about 5 decades ago. What this assume is that here defects cause a single line to be either permanently stuck to logic high or logic low and that we call as stuck at 0 fault or stuck at 1 fault that means here we assume that any line in a circuit like for example if I have this AND gate. So, it has 3 lines. So now here any line this line can treated as due to defect this can permanently connect to or logic 0 that means ground or permanently connect to your power supply. So that is the very simple model we can use. Now here there are 2 questions. First thing is how good this model is and second is what does this bias. So, first let us look at how good this model is. So, let us say you have a tutorial logic. So, you have transistors now here the possible defect may be this transistor is sorted. If this transistor is sorted then now here what can be be the logical manifestation of this defect that this transistor is sorted. Then of course if this source in that case here this node will always see the ground potential. So, that the ground potential means here irrespective of what you apply at the input signal lines always here you will see 0 or ground potential at line C. Hence here I can say that this physical defect transistor is sorted. We can model as node C or this output line can is stuck to logic 0. In the same way here if I say that this input is open if this input is open in that case here this transistor would not conduct and then here the fallout effect of that is you will see node C is always at Vcc and hence here that you can say that node C is stuck to logic 1. This is the case when in the TTL technology. Look at the MOS technology say in NMOS say first look at if this transistor is sorted. So, first look at if this transistor is open. If this transistor is open in that case here always you will see that this point or node C is always at Vdd. Hence this defect you can model as node C is stuck to logic 1. And if this transistor is sorted in that case here the effect of that would be like here because this is sorted. So, that means here this will look like the node A is always grounded. If it is always grounded then you will see the transistor is always conducting and hence that is same as your transistor sort. So, now here this because the actual defect is this transistor is sort, but now here I can model that as stuck at 0 fold here at logic at node A. So, now here if you see that there are couple of defects which can be modeled as same fold. So, now here so now this gives you a big picture that here various defects can be modeled as logical folds. Now good thing about the logical fold is that we are assuming that every line can stuck to logic 0 or logic 1 and by and large most of the defects in bipolar technology and NMOS technology we can model as stuck at folds. So, this works reasonably well for bipolar and NMOS technology it is less good for CMOS because couple of defects it cannot a couple of defects cannot be modeled as stuck at 0 or stuck at 1 fold then here we have to supplement that model with another fold model that we have to use while we are testing. So, this gives you a sense that how good this model is whether we can model various defects as folds or not. Now the question is if I model these defects as logical folds then what it bias. So, now here let us look at a 4 input NAND gate it has A, B, C, D as input and Y as output. Now as we say that here we can model the defect as a logical fold and logical fold assume that any line can either stuck to logic 0 or stuck to logic 1. So, now here and keep in mind that here we are assuming single stuck at fold. So, that means here there can be only one fold in the circuit we will discuss whether this assumption is reasonable or not in a minute, but assume that here there can be only one fold at a time in the circuit. Now how many folds can be there? So, now we have 5 lines. So, there can be 10 folds because every line can stuck to logic 0 or stuck to logic 1. So, now here like line A can stuck to logic 0, line A can stuck to logic 1, line B can stuck to logic 0, line B can stuck at 2 logic 1, line Y can stuck to logic 0, line Y can stuck to logic 1. Now the question is how I test these 10 different folds? Now here let us say I apply a test some input let us say I apply 1, 1, 1, 1 as input A, B, C, D what it can test? If I apply 1, 1, 1, 1 then if say if in this circuit if I apply 1, 1, 1, 1 here and say I have stuck at 0 fold here. So, if there is no fold in that case the output would be 1, if this fold is there what will happen irrespective of what I apply here this point is always at logic 0 and by application of this 1, 1, 1, 1 I will get output as 1. So, now if you look at the output of the circuit for the fold free circuit I will get output 0 for faulty circuit I will get output 1 and these are distinguishable output. Hence, I can say that this input can detect this fold stuck at 0. So, now this way here we can say that this will detect stuck at 0 fold to stuck at 0 fold at line A. Now what about the stuck at 0 fold at line B this is B. If I again here if I if there is no fold in the circuit my fold free behavior is 0. Now if there is a fold here and we are assuming that there can be a single stuck at fold. So, now this node would be this point would be permanently connected to ground hence here the fold at line B. Out behavior of faulty circuit would give you output 1. Hence, here again this is also distinguishable. So, that means here we can also detect B stuck to 0. This way we if you work out we can also detect C stuck to logic 0, D stuck to logic 0 and Y stuck to logic 1, because here your fold free behavior is 0 and then if this point is stuck to logic 1 and then always it will give you output 0. So, it is a distinguishable fold free and faulty behavior. So, this vector can detect these 5 different folds. Now if I because I have 10 different folds if I apply a vector 0, 1, 1, 1. Now what will happen if I apply 0, 1, 1 what it can detect? So, if I apply 0, 1, 1, 1 my fold free behavior is 1. What it can detect? If there is a stuck at 1 fold here. So, under faulty condition this input will permanently tie to VDD or logic 1 and hence the behavior of faulty circuit will give you output 0. Hence, again this is distinguishable faulty and fold free output. So, this can detect A stuck to logic 1. This can also detect Y stuck to logic 0, because here your fold free behavior is 1. So, if Y is stuck to logic 0 in that case output would always be 0. Hence, you can distinguish the fold free and faulty behavior. So, you can also detect Y to logic 0. So, this vector can detect 2 more folds. Then in this way if you apply 1, 1, 1 this can detect B stuck to logic 1, Y stuck to logic 0. If you apply 1, 1, 0, 1 then this can detect C stuck to logic 1, Y stuck to logic 0. If you apply 1, 1, 1, 0 you can detect D stuck to logic 1 and Y stuck to logic 0. So, now here if you look at this how and this covers the your entire fault list. These are the modelled folds. So, that means here if I can detect all these 10 different folds I can say that my circuit is fold free, because I covered all modelled folds. Now, how many test vectors we need? We need only 5 vectors. If you apply exhaustive test set in that case you need 2 raise to the power 4 that means 16 test vectors. Now, there is a use reduction to have reduced almost to one third. Now, so and this is sufficient test set to test all the folds in the this circuit. So, now here if you look at more closely what it brings you on your plate? See here your test size will reduce to n plus 1 from 2 raise to the power n, because here you have 1, 2, 3, 4, 4 lines, 4 input lines and so now here and you need 5 test. So, now here that number is 4 plus 1 is 5. You do not need 2 raise to the power n. So, that this is big thing. You are converting a problem from exponential complexity to linear complexity and we discuss that here this exhaustive set we cannot apply, but here anything which is linear we can apply. So, that means here if you have a circuit with say n inputs or that may be 100 in that case if I can convert that problem into n plus 1 it is sufficient for me. So, that means 101 test I need to apply this. So, in this case this fits well. If you have a circuit which is fan out free and single output then again you can say that here you need a test size of n plus 1 test. If there are fan outs in that case here this number will slightly increase by the number of fan outs you have in the circuit, but for fan out free circuit again this relationship holds good. Hence here we can say and if there are fan outs in that case here again this will increase by the number of fan outs. So, means the big thing this brings into our plate is you are converting exponential complexity problem into a linear complexity problem and that is big thing and that is why here we do not target defects we target faults which are logical manifestation of the defects. As I mentioned in last lecture that defect oriented test is still open problem and some of you may provide some good solution which can advance state of the art. So, now here we are converting this exponential problem into linear problem. One thing again to notice is that in this if you look at it closely one test can detect multiple faults or one fault can be detected by multiple test. So, there is no uniqueness relationship between the test vector and faults. So, this gives as opportunity to reduce the number of number of test. Now here our objective is to find out smallest test set that can cover all the faults. So, now here if say this vector can detect y 0 in that case I can choose that and then I do not need to target y 0 again. If this vector can detect 5 faults in that case here these 5 faults again I do not need to test. So, now here there is no uniqueness relationship between the faults and test vector. So, now here say look at this circuit this is a very popular circuit all of you know this is a NAND-NAND implementation of XMOR gate. So, this fault this circuit has 12 different sides. Now here another very important thing that I would like to bring to your notice is that this fault at stem of a fan out point is different from fault at the fan out branches. Because here they may have different manifestation this output though here these outputs are reconversing, but here this may possible that they would not reconverse and this output may go to some primary output and this fan out branch can take you to some different primary output. So, now they have different manifestations. So, in terms of logical error hence here we treat the fault at the input of a fan out point and output of fan out point differently. So, now here we have total 12 different sides hence there can be 24 different faults. Now means working in the same direction earlier we discussed that here if there is a stuck at 0 fault at line h and if I apply input as say 1 0 in that case will it detect this stuck at 0 fault it will because here your fault good circuit value would be 1 and then here faulty circuit value would be 0 and hence this can detect this particular fault. So, now means here we by modeling these faults as a single stuck at fault we can generate a compact asset and we have seen that we can reduce the problem from exponential problem to the linear complexity problem. So, the so first fault model that was given way back about 5 decades ago is the single stuck at fault model that assume that only one net can stuck to logic 0 or logic 1 at a time and so now here the number of faults that you can have is twice the number of nets that the number of lines that you have in your circuit that is linear and that is why we are converting the problem in linear complexity problem. Now, we can argue that how reasonable this assumption is do you think that always we can have only one fault in the circuit or one defect in the circuit though multiple defect can manifest as the same fault as well. So, that may not be reasonable. So, now what is reasonable? Reasonable is that there can be a multiple defects multiple defects may result into multiple faults. Now, you need to target a multiple stuck at fault rather than single stuck at fault. Now, if you look at the number of multiple stuck at fault if assume that there are n number of single stuck at fault or in the circuit or n number of lines or n number of lines or nets you have in the circuit out of the this n line now here any line can give you may be be the fault free. So, that may be fault free or that may may may stuck to logic 0 that may may stuck to logic 1. So, that any line can be be in three states fault free stuck to logic 0 stuck to logic 1. Now, if there are n lines how many total permutations can be be there in the circuit that would be 3 raise to the power n the out of these 3 raise to the power n instances only one instance would be fault free when all the lines are fault free all other instances are fault instances. So, now here the number of fault instances would be 3 raise to the power n minus 1. So, that that means that there can be 3 raise to the power n minus 1 multiple stuck at fault in the circuit again here this problems this problem converts to the exponential problem and all these 3 raise to the power n minus 1 fault may not be targeted. But people observed that if you because of known unique relationship between your fault and and test vector then you are likely to detect large number of multiple stuck at faults. So, in other word if I say test all or or 100 percent single stuck at fault I am likely to detect 80 85 percent multiple stuck at faults using the same test pattern that gives us big relief. And so now this is the standard practice in the standard in the industry that they are using single stuck at fault model and they though that can cover large number of multiple stuck at fault. Now, the so this is one of the very popular and common fault model industry uses. As I said that this single stuck at fault model can can model most of the the defects in TTL, NMOS and large number of defects in CMOS. There are some faults which are like transistor open and transistor sold. So, transistor stuck open, stuck sold fault which are really not modelled by single stuck at fault in CMOS logic. So, that means here we have to to to test for those faults as well and then here another fault model was given for for those kind of faults which are which are not covered by single stuck at fault or the the the transistor stuck open and and the stuck sold faults. Then other kind of circuit that we have in practice are memory. Now, if you look at memory, memory does a very specific operation or job what it does is it stores value what you want. So, logic 0 or logic 1 it retain that value until you would like to rewrite it right. So, what you want is that if you would like to write 0 it should write allow you to write 0 if you write 1 it should allow you to write 1 and it should retain that value until you rewrite that. So, these are so because this does or this performs a limited functionality. So, rather than go going for stuck at kind of fault which is very appropriate for a random logic we go to functional fault model and then then here we model those faults as like whether memory is able to write value 0 or not whether memory is able to write value 0 to a cell or not and whether it is able to retain that value or not. So, these are some of the functional fault model that we use and this reduces the complexity tremendously and hence these functional fault models are being used for memory. Other kind of circuit that we may have in practice are the programmable logic arrays. In that means other than stuck at faults there may there are some other faults which may appear which are unique to PLA those are like here there can be a cross connection between the two lines. So, cross point or bridging faults the circuits like processors perform many operations, but still it is the set is limited like a processor is supposed to execute a couple of instructions those are finite in number and the behavior of each and every instructions is well defined. So, now here what we can do is rather than going for stuck at fault model we may target the functional fault model that means here how instructions are being executed whether it executes that correctly or not. There are some faults which are like which does not lead to the malfunctioning of the circuit if you do not care about the frequency of operation, but they result into malfunctioning of the circuit if you test at certain frequency that means here if you operate your circuit at slower frequency your circuit may work perfectly fine, but if you operate at the designed frequency your circuit may not be able to operate at that frequency and there are there are couple of fault model which were developed to test for such kind of performance oriented fault and those are popular model or transition delay fault model and path delay fault model. Other class of circuit that we have in practices analog circuit unfortunately till today we do not have any fault model like single stick at fault model which was given for digital circuits. By and large the analog circuits are tested against specifications though there were attempts and then people developed some alternate test method that by observing some of the derived parameters of the circuit and which are which reduces complexity significantly. So, these are the various common fault model we use single stick at fault model is pretty common. So, most of the industry do test their circuit for all single stick at fault and delay faults and of course, analog circuits are tested for the analog faults and memory is always tested for the using functional fault model. Now, here let us concentrate on the single stick at fault model which is pretty common and all the circuits are tested for single stick at fault. Now, the question is how I should generate test for each and every fault each and every single stick at fault in the circuit. So, if you have N line in the circuit or N net in the circuit you may have 2 N number of faults. Now, here the question is how I should generate that test. So, say you have this circuit which we discussed earlier a 4 input NAND gate A, B, C, D are the input if I say I have stick at 0 fault here. Now what you means how you can detect that if as we discussed that if I apply 1 1 1 1 as input here always I will get faulty and distinguishable faulty and fault free behavior at the output and hence you can detect that fault. But now I have just reverse problem of the earlier one. Now I have fault at my hand and I want to find out a test vector that can detect that particular fault. What I need that my basic requirement is that whatever input test input I apply that should produce distinguishable faulty and fault free output. So, now here this net is a structural logic 0. Will it ever produce a fault at fault distinguishable output if I apply 0 here it will never produce irrespective of what I apply at B, C and D. Hence this is ruled out. Now what I should apply here if I apply 1 here in that case there is a possibility that it may produce distinguishable fault free and faulty output depending on what I apply at B, C and D. If I apply B as a 0 in that case it will never produce distinguishable fault free and faulty behavior. In both of the cases it will produce output as what would be that output that output would be. So, I apply 1 0 1 1 and output would be 0. So, in both of the cases it will be 0 faulty and fault free behavior. So, now what I want that the line which is stuck to some logic value 0 or 1 I should have at least inverse or opposite value to that. So, now if it is stuck to logic 0 I have to have 1 if it is stuck to logic 1 then I have to have 0. And as I said that this may potentially propagate or may produce faulty and fault free behavior at the output provided that I assign the another input or side input to this gate as known controlling value. So, what is the controlling value of a gate? The value which always determine the output. So, if I apply 0 value to any of the input output would be determined by that our output would always be 1 irrespective of other values. So, now I have to apply known controlling value that what does that mean that if I apply known controlling value to other inputs that means here output would be determined by this input only. So, if I apply opposite value then here output would be distinguishable. So, that means here I have to have 1 1 and 1. So, what it can tell you that if I want to detect a fault here what should be my test vector? First I should have different value or opposite value to the faulty value at that faulty side and other inputs must be at the known controlling value. This is the basic criteria based on that we have to generate a test for each and every fault. Now, there are two mechanism one is the algebraic way. Algebraic way is based on the Boolean algebra. So, if you look at Boolean algebraic manipulation say if you have a circuit with n input x 1 to x n then output of that circuit would be f would be given as f of x 1 to x n. This may be x 1 x 2 plus x 2 x 3 plus x 1 x 2 x 3 plus x 3 x n something like that. Now, always I can decompose this output or this function in sub functions with respect to an input say if I guess all of you know the Shannon's expansion theorem what it says that if I want to decompose this function with respect to x 1 I can write that x 1 dot f of when 1 x 2 x 3 x n. So, that means here this function is the output of the circuit when x 1 is equal to 1 plus x 1 can be 0. So, x 1 bar dot f of 0 x 2 to x n. So, that means here this function would be output of the circuit when x 2 is x 1 is 0. So, that this way I can decompose a circuit. What I want is that if there is a I want to have distinguishable fault T and fault behavior. Now, depending on your fault location and nature of fault in order to test as I said that we have to apply the opposite value to the fault T value at the fault side. So, now if fault is stuck to 0 in that case here the fault T behavior would be given by this one and in order to test that here I have to apply the opposite value that means I have to apply one then your fault free behavior should be given by this one. So, now here what I want this should be distinguishable that means here the XOR of this function and this function should be should evaluate to 1 and that XOR operation is defined as Boolean difference. So, that means what I want is that here this Boolean difference must evaluate to 1 and I have to apply opposite value of the fault T value at the fault side. So, now here if I say that line say x i is stuck to so, is stuck to logic 1 in that case here. So, if x i is stuck to logic say 1 in that case here I have to have opposite value. So, that means here x i should be 0 and del f upon del x i this should also evaluate to 1 what I can say is that here your x i bar dot del f upon del x i should evaluate to 1 this is the condition to detect x i stuck at 1 if x i stuck at 0 in that case what I want that x i should put to value 1 and it should produce the distinguishable fault T and fault free output. So, that means here del f upon del x i must be 1. So, what I expect is x i dot del f upon del x i this should evaluate to 1 this gives you the condition to generate test vector algebraically. So, let us look at example. So, these are the two conditions that I have already discussed now let us look at this circuit. So, the output f can be given as x 1 x 2 plus x 3 now you have to determine or detect stuck at 0 fault at x 2. So, now what should be the condition first thing is x 2 should be assigned with value 1 if it is stuck to 0 if and it should be assigned as value 0 if this net is stuck to logic 1. Now you so now and then here that fault effect should be propagated to the primary output what are the conditions that Boolean difference with respect to x 2 should evaluate to 1. So, that means here this x 1 what is the Boolean difference with respect to x 2 that is x if you put x 2 equal to 1 in this if this will evaluate as x 1 plus x 3 and if you place x 2 equal to 0 in that case this will evaluate to x 3. So, this would be x 3 x 4 with x 1 plus x 3 that will give you x 3 bar x 1 this should evaluate to 1 when this can evaluate to 1 this can evaluate to 1 only when x 1 must be 1 and x 3 must be 1 this gives you the propagation criteria. And so now if you want to generate a test for x 2 stuck at 1 in that case here x 2 must be 0. So, now here x 1 must be 1 x 2 must be 0 and x 3 must be 0 this gives you the detection condition for stuck at 1 fault at line x 2. Now for a stuck at 0 fault x 1 must be 1 x 2 should be the opposite value. So, that means here that should be 1 and output must be x 3 must be 0. So, this is the detection criteria what if this x or this your Boolean difference is 0 that means that your circuit is not able to transfer the fault effect to the primary output what does that mean that this input or this signal is not contributing in making a decision. So, that means this input is redundant input hence though those faults are known as redundant faults. So, now this methodology will either give you the test vector or it will say that this fault is redundant fault and now here you do not need to test for that because here anyway that fault may not have any implication in your functioning of your circuit hence even if that fault is there you are ok with that. So, now this will give you the faulty so test vector or identify fault as redundant fault. Hence I can say that this method is a complete method this can identify fault as a testable fault and give you the test vector or identify fault as untestable fault or redundant fault. So, now we compute 2 different parameters one is known as fault coverage another is known as fault efficiency fault coverage is defined as the number of detectable faults divided by the total number of faults. So, same way you have total 1000 faults and 990 faults are detectable, but here 10 faults are not detectable in that case here your fault coverage would be something 990 divided by 1000 into 100 that becomes your 99 percent. Why they because here 10 faults are redundant they are coming from the redundancy in the circuit sometimes you have redundancy because of ease of manufacturing or because of ease of design like for example, if you design a 4 bit adder you do not design that 4 bit adder with 3 full adder and 1 half adder generally we design with 4 full adders. So, that means here one of the half adder is redundant in that design, but because VLSI favors the regularity and hence we prefer to have 4 full adders and that so that redundancy may so due to that redundancy we get lower fault coverage. We define another term or metric to evaluate how good our test is that is referred as fault efficiency. Fault efficiency is defined as total number of detectable faults divided by total number of faults minus total number of redundant faults though those you identify as redundant faults. So, like here now in this example we say that 990 faults are detectable and 10 faults are identified as redundant faults. So, that means here this is 1000 minus 10 multiplied by 100 this gives you the 100 percent fault coverage. So, that means here we are able to detect all the faults which are potentially which are which may cause small functioning of the circuit and this Boolean difference method or algebraic method can give you always guaranteed 100 percent fault efficiency. Now, why I defined these two metric why not only one metric what additional information my another metric gives you fault the difference between the fault coverage and fault efficiency gives you how much redundancy you have in the circuit. So, now, we identify the kind of redundancy so now in the circuit and then if it exceed beyond the limit certain kind of redundancy is admissible to us say may be 10 percent redundancy in the circuit may be admissible. So, now if redundancy is below 10 percent it is otherwise test engineer has to report this information to the design engineer say that look your redundancy in the circuit it is 30 percent are you ok with that if he is not ok then he has to resynthesize his circuit and bring down the redundancy in the circuit. So, again this is the another task of test engineer to identify redundancy in the circuit and report it back to the test design engineer if it exceed beyond the certain limit or beyond the tolerance limit. As I said that here due to certain reason like here means in order to minimize the propagation time or delay of the circuit or if it results into regular structure here we deliberately introduce redundancy sometimes in the circuit. So, this is the algebraic way to generate test set. Now, the problem here is always we need to do bullion manipulation and bullion manipulation is not feasible for fairly large design which has say several 100 million kids. So, this approach is not scalable in order to have scalability here we have to go for algorithmic methods and some of the algorithmic methods were proposed in the literature which are based on the past sensitization algorithm those were D algorithm which was first complete algorithm given by Roth from IBM in 1966. Then there were improvement on that method and the another algorithm which is known as Podem and that was given by Goyle from IBM again in 1981. Then and this algorithm Podem was almost 100 times faster than D and then the another faster variant was developed by professor Fujiwara from Osaka University at that time that was known as FAN in 1984. So, these are the three basic algorithms and most of the today's CAD tools are largely based on either Podem or FAN algorithm. Then there were several improvements in which they tried to support these algorithms by learning from the circuit and those are two of the popular algorithms are Socrates and Spirit. All these algorithms are based on path sensitization. So, this path sensitization based algorithmic method to generate test we will cover in the next lecture. With this I complete this lecture here. Thank you very much for presence full listening.