 So, in this session we will see a lot about power, we will see the methodology, we will see how it all is power. So, the agenda is I will introduce the tool called power compiler, power compiler is part of the synopsis design compiler tool, it is used to, so it is just you can say that set of features available inside design compiler, which lets you work on the power, then we will see the design flow, power compiler design flow, we will see how it fits into the synopsis synthesis flow, then third we will see what are the, how the power is modeled, what kind of different power number would be be interested in and how they are calculated. We will see about, we will learn about switching activity or SAIF is a five format that is used to pass on that information the switching activity problem, we will see what is switching activity, how is it used, we will see how do we analyze power number, how do we go through the reports, then we will see a very interesting implementation, interesting and one of the most useful for single voltage design power compiler cooperating, and lastly we will see how power is optimized in design, so let us start with the introduction, so power compiler is part of the synopsis design compiler family, it is used to perform both RTL level and gate level power optimization and gate level power analysis, via the power analysis cannot be performed on RTL, it will become very clear RTL in the later slides also, but let me explain it here itself, if RTL is it does not have gates right, RTL has very low, for example, very low RTL has always more, but it does not actually have gates, and there is no concept of the reporting power on RTL, you can actually analyze RTL to reduce power, you can employ some techniques in RTL it says to reduce power, but what actually is the power number you cannot know because power numbers are gate and technology dependence, so we need a netlist to know the power number, and that netlist should be mapped down to one of the technology that will which will contain the power numbers right, so logically you could optimize power on RTL, but you can do power analysis only in data, so power compilers various power there are lot of power reduction techniques in power compiler, most famous being clock waiting is something called operating isolation multivit, leakage part power optimization very very very important thing, it is a very useful thing that is relevant in lot of designs, and gate level power optimization again there are two techniques, so there are some techniques which are very useful very used extensively for single voltage design which we will see few of the techniques we will see, then there are a very a lot of advanced techniques which are used for multi-voltage design, okay, a chip will have different voltages for different sections of the chip, we will not go into that because there is a separate methodology for that, separate ways of implementing that, but that is the scope of the scope, so we will be focusing on the power optimization and power analysis of the single voltage design, and what techniques will be involved, so the methodology for, so power is usually of two types, we divide the power of the two types, static power and dynamic power, so the methodology involves how do we, so the analyzer leakage power, and power compiler helps us to reduce the leakage power by using multivit threshold power optimization power system, so each of these terms what I am discussing here, we will see details of it in the later slides, then there is something called dynamic power optimization, which uses the ways are by inserting clock gating cells, there are a lot of options available when we insert clock gating, operand isolation, gate level power optimization, then you can, we can do RTL level power optimization, again inserting clock gating on that, we can do gate level power optimization by using multivit threshold voltages, dynamic power optimization can be done by reading the picking activity, again it power compiler gives us ways to analyze power in both RTL and gate level, using simulation data actually, so do not worry some of these terms are not clear, they will become clear as it is, so the design flow is pretty simple in fact, design flow at both RTL and gate level stage is same, there is the analysis part, so the simulation is very important when we talk about power numbers, because any let us say I have a design, I have an SSM and I would write, so the design cycle would be like this, you will design the SSM and you will design a test bench that will test the whole SSM, there will be a mission mode test bench, that will take this SSM through a number of test cases, which will limit the real world function right, which will limit the real world scenario, so we will exercise SSM, we will give inputs in such a way that, those inputs the similar inputs are expected to be given to SSM real world output, so this this stimulus will actually determine how much power that SSM would take, simulation is a very important part of power analysis, so because simulation gives us something for switching activity, we will be in the details of the data, so simulation provide this as switching activity, so we can use the switching activity for analyzing, plus our compiler can use the switching activity to actually also optimize the power, so at both RTL level and gate level right, so this is the optimization, so it is very very similar to a regular design compiler optimization, so the only thing extracts power, acknowledge that to be an RTL design are tables here, so we will need that definitely, we have to just enable power optimization, we will see how we can do that, then we do synthesis and power optimization, so see simulation here is feeding this SF5, so this is called switching activity five, it goes as an input before the synthesis takes place, so now synthesis has what it has, it has technology that it knows the power number, it has a switching activity, so it knows we will see what what information does the switching activity provide, and now it can do the power app, it can do power optimization, then you can use some reporting to report power, then we get a gate level power optimized, right, but there is one more option is that, so this simulation is taking taking as a place of the RDA, we can again simulate this, we can apply the same stimulus to the necklace as well, and that we can also get the, so after the design is routed we also get the capacitor information, we can feedback this information, and do further accurate power analysis, now let us talk about the basics of power, what is what are the power terminologies we use, what are the power, how do we compute the power number, so power is drawn from the voltage source that will attach to the VDD of the power, so it is very clear from the first instance of the power, the higher the VDD, the higher the power number, so P is equal to I into V, V is nothing but VDD here, the current drawn from the power supply, this is the reason that most of the, now as the technologies, as we move on to the only the same, so piece of my phone, the VDD is reducing, so earlier in 90 nanometer odd or 90 nanometer odd, the VDD went up to 1.2, 1.5, but now we are in the range of 1 volt, 0.9 volt, so as we decrease VDD, obviously the power is decreasing, so for example, handwritten application type of phone, V chips will not hardly there will be any chip which will require more than 1 volt for digital source, right. So instantaneous power is I, I, IDD dependent on time into VDD, VDD 6, energy is again integral of power VDD, so integral of power with respect to time, so we be substitute the values of I and V, average power is energy divided by time, so it is 1 by 1 by T, we just substitute the value of energy here, so this is the, this is the average power, now we use this equation to calculate all other power numbers, now there are the power numbers are divided into two types, static power and dynamic power, again dynamic power is divided further divided into two types, switching power and internal power, we will see what each of these will be, static power is consumed even when the chip is switched, that means even if no activity is taking place in between, it consumes a bit of power, this is called standby power, let us say for example, your mobile phone, in fact mobile phone works or, in fact mobile phone even when it is not doing anything with the smart phones, we lot of tasks in the background, but let us say let us talk about the feature phone, which do not have run so many tasks in the problem, even if we, we are not doing anything, we are not talking to anybody, we are not listening to any radio, the chip consumes power, right, so this is called static power, that means even when the chip is in question condition, what is the largest you already know by experience that, the standby power, the standby time for feature phones is much longer, it phones into like 5 days, 10 days and so on, so it is understood that static power is the, the lesser known, the lesser culture here, but the most, the largest percentage of static power results from source to train and with the shrinking technology, so it depends on with the most, the single most important factor here is the VT, that is the threshold voltage of the device. So, with shrinking technology, with shrinking with VT going lower, the VT is also going lower, VT these are the equations for the drain to source current, the substantial leakage current and as we reduce VT this current increases, what it means is that, as we go as a technology stream, the leakage power contribution is increasing. For example, 45 nanometer cells will be more VT than the 90 nanometer cells, because the VT would be lower, you can, you can verify from this, so this is the VT formula, VT 0 minus beta VDS, this is the, this part here, this part of the equation here is, is related to the effect of the device voltage. So, usually the, if you, if you go back to the equations of PMOS and NMOS, the transistor equations you will see that, usually at the start of the analysis, understanding we assume that VFB 0, the body affected 0, but you could have a case where the body voltage is not 0, so there will be some difference between the voltage and the voltage of the body, so this takes care of that effect, this takes care of the drain to source, this depends on the drain to source voltage. So, VT, the lower the VT, so the principle is that the bottom line is, the lower the VT, the more leakage the device, right, the lower the VT, the higher is the IDS, and therefore, the lower the VT, the more leakage the device, but the device is faster. So, what it means is that, the technology that we guys who open the technology model, now have some options, right, they can either build a device which is fast, but then by playing with the VT, but then device is also faster, but it is consumes more power, it consumes more leakage power, again you can raise the VT and make the device lower, but then it will be good for low power output. So, we will see more of this in the coming time, right, how is this used to power. So, again I stress that, static power in present day, static power is or we use the term leakage power is caused due to some threshold, so should be a substrate, threshold leakage, this is the leakage power is the majority component in the static power, right. Now, comes the dynamic power, dynamic power two types switching and internal, what is the switching power? So, dynamic power is required to charge and discharge both capacitor switches on that output switch. So, for example, look at looking at the inverter, we see that inverter it during the operation which is from 1 to 0 or 0 to 1. So, once I get involved rising and falling output, on rising output the we no see gets charged up to VDD. So, charged use is equal to CVDD is required, when the output falls to charge, same charge is done to go. If we take a time period of T and the switching frequency to be SSW by T times SSW, it gets repeated, right, the charging and discharging of the local. Let us see how dynamic power is calculated. So, again we take the same equation 1 by P IDD VDDT, the T is T is kind of a constant here, it comes out again we realize the equation we multiplied by P SSW. So, you could say that 1 by T, 1 by T is nothing but SSW and integral of IDDT is comes out again we see CVDD. So, the equation out here this is the final equation to be written in this, CVDD is equal to f over 4, right. Now, so what does the dynamic power dependent on dynamic power? Majority depends on obviously, the VDD is lower the dynamic power is lower, it depends on the load capacitance, the higher the load capacitance the higher the power and this is the most important thing SSW, this is the switching activity. More frequent a signal switches, the more frequent the gate switches more is the power, right. So, signals what is the signal that switches more? It is the clock, what is the signal? So, the switching frequency of the clock is high, it toggles like twice per cycle it goes to high goes low, again the higher frequency clocks will have more switching activity compared to lower frequency clock per unit of time. So, high frequency clocks that is why clock networks, high frequency clock networks can view most of the problem of all, right. Data signals comparatively switch lower the switching frequency of data signal is more as high as clock. So, let us say the system of frequency is f, let the switching SSW is equal to alpha f where alpha is the activity factor. Now, if the signal is the clock alpha is equal to 1, what it means is that if the signal switches twice per cycle alpha is equal to 1, if the signal switches once per cycle alpha is equal to 1 by 2. Please remember this dynamic gates switch either 0 or 2 times per cycles average alpha we take to be 1 by 2. Since, when a switch signal switches once per cycle alpha is equal to 1 by 2, signal switches twice per cycle like clock alpha is equal to 1, for dynamic gates they either switch 0 or 2 times if this switch 2 times alpha is equal to 1, alpha is equal to 0 here average alpha is 1 by 2. Static gates depend on the design, but typically default values have been seen to be alpha is equal to 0.1. This is only for data signals not for clock, for clock it is special data is equal to 1 right. Data signals the typically switch less. So, alpha is just a number based on some statistics. So, now the dynamic power equation becomes alpha CVTD square f. So, we replace SSW by alpha f, f is the clock frequency now. What happens to data signals? For data signals we would be concerned about the clock they are related to. For example, we write in all this block always a positive CTD we captures some data on that clock. Now, that data will actually the meaningful clock is the same clock it is capturing the data now not any of the clock. Let us say you call the design in multiple clocks. So, each data signal will have a relative clock right. The frequency of that clock should be taken into consideration. So, let us say a data signal works for now 100 mega, you have let us say 2 blocks in a design 100 mega, then 200 mega not all data signals will work on 200 mega. Some of the data signal will work on 100 mega, some of the data signal will work on 200 mega right. So, data this is why the data is also also connected with a clock signal. Second type of power dynamic dynamic power is internal power when transistors switch both NMOS and PMOS network are momentarily connected. This leads to a flip of short circuit. So, whenever this is the switching involved. So, let us say for an inverter let us go back to NMOS. Whenever there is a switching involved. So, let us say NMOS is turned on PMOS is off in static condition output is 0 if NMOS is on. When output when input changes state NMOS starts going from on to off condition, NMOS starts going from off condition. Now, there is a overlap of time during which both NMOS and PMOS are off. This leads to a burst of short circuit time. The short circuit time although is less for one device, but consider thousands of or hundreds of thousands of device on a strip switching state right. So, for for a bit chip this becomes significant this kind of short circuit power becomes significant. If the rise for times are comparable for input and output and for faster frequency time typically this would be less than 10 percent of dynamic power. So, still the internal power is less prominent than than the power that is based on switching activity which is the switching power right. So, dynamic power. So, in terms of in present day chips the most the most important factor is dynamic power which is caused by switching that means charging and discharging of load capacitor. Second is dynamic power which is internal the short circuit power. Third is the leakage power that is dependent on the that depends on the substantial leakage right. So, these are the three major power factors. So, so internal power is again so internal power is a more generic term short circuit power is type of an internal power. So, internal power by definition is any power that is dissipated within the boundary of the cell inside the cell not depending on the load capacitance right. During switching circuit dissipates power by charging or so in fact, a complex gate will have lot of source and drain capacitance which is inside that gate not not counting the outside load capacitance right connected to the output. So, all these capacitance is internal gaps are charged and discharged during switching. So, this also counts as internal power for circuits the internal power depends a lot on the transition times. If the transition times are faster the overlap window during which P and P network and N input cross analytically form is shorted, but for slower transition times you can operate all the diagonal AC. For slower transition times this time expands the overlap time expands. So, if you have slow transition times it can even consume up to 30 percent of the total power dissipated power which is very very significant. This is why faster transition so, faster transition times are good for everything faster transition time means the delay is faster because the output delay depends on the output cap and input transition time. So, faster input transition times means faster pass I mean input delay and they also means less internal power right. So, the short circuit power as I told before short circuit power is the majority component here in for internal power, but for more complex cells or the charging and discharging of internal capacitance might also be the source of dominant source of internal power. So, this is an illustration for shorter ISC the leakage current sorry ISC the short circuit current I IK is the I LK is the leakage current, leakage current is a substation of grade to source leakage short circuit current only happens during the B switching and again there is a load capacitor. So, ISW is the switching. So, there are three current responsible for three separate power. Switching current again I will repeat again switching current SW with charges and discharges the load capacitance is responsible for dynamic power switching short circuit current is responsible for dynamic power internal it is caused when P and N are simultaneously on during switching for a short period of time leakage current depends does not depend on switching leakage current is the is the current that is that goes from drain to source during the substation is that means, so it depends highly on VT if VT is lower the special leakage is higher if VT is higher the special leakage is lower it is also called leakage power that is why it is called leakage power or power. So, it is called leakage power and leakage power. So, dynamic power you need to be sure what type of power it is the switching power or internal. Again the remains this static power does not depend on switching that is the power depends on switching dynamic depends on switching nothing does not depend on switching static is the two sent gates this the case where the chip is not showing any circuit. Now, let us see how does power compiler calculate leakage power and leakage power is pretty simple does not depend on any switching. So, what power compiler needs to do power compiler needs for each cell power compiler just needs to read the numbers from the. So, what you can do is at this point of time after this again you can go back open your standard cell library and see that every cell start at the combination cell every cell will have some power number one of the power numbers is designated as cell leakage power. So, that is the leakage power of that device of that cell for each such cell in your design. Now, let us say your criteria design has 10,000 gates you know combine the combination and sequential combine together. So, each of those 10,000 gates power compiler just needs to go to the library grab the cell leakage power number and that is the total leakage power of your design. So, pre leakage total nothing but summation of leakage power of each cell ok. So, libraries provide single leakage power if they can provide single leakage power for all cells in the library by using the default cell leakage power attribute. So, a very rudimentary very first cut library may have a default cell leakage power attribute for this will apply to all the cells in the design or if you want to go more specific which is the case because a 2 input AND gate will have probably have less leakage than a 3 input AND gate for example. So, multi input gates will have like 3 input gates will have probably have more leakage than 2 input gates because the number of devices are all in the library. So, so there is one default cell leakage power attribute in the library and then there is a cell leakage power attribute library attribute which is first cell. So, first cell leakage power is denoted by cell leakage power attribute if this leakage power attribute is missing or negative it cannot be negative through the science the value of the default. So, if for a particular cell the tool does not find a cell leakage power attribute it will look for default cell leakage power attribute if it is not available even the default numbers are not available it does not have any choice, but to give it to the there is also something called a state dependent gate. Now, let us say for an AND gate if you go into more specifics the leakage power will be different for the 4 cases. What are the cases? The cases are the 2 inputs can be the 0 0 0 1 1 0 1 1. So, there are 4 states. So, AND gate will probably have different power for each of those gates. So, you can also have a state dependent cell in the power in the library you can open your library and see if there is any state dependent gate we will probably see in the lab we will we will go into the library and see how the power is represented in the library. So, again to calculate the cell leakage. So, now what happens is there is a state dependent gate right. So, if you do not if you do not give any other information to power from power it will assume that all these states are equally property. So, what it does is that it is taking the average of all these states right. So, to calculate cell leakage power it determines the unit first of all it determines the unit based on the leakage power unit attribute. Then it states for the leakage power attribute the leakage value of. So, for each state the leakage power is multiplied by the percentage of total simulation time at that stage. Now, let us say you are able to tell power compiler that for example, for an AND gate is able to take power compiler that ok. One of the states is more likely to happen in other states this is called again this is the nothing, but switching activity or form of switching activity where you are able to and they are doing that one of the states is more likely to happen in the other state state. In that case the leakage value of each state is multiplied by the percentage of total simulation time at that stage and then sum. So, it is a weighted output right in case who data is available is just in the model. So, if the state is not defined if you define the value of cell leakage power is used to if a particular state is not defined the value of the cell leakage power attribute is used to obtain the quantity. Let us take an example. So, now this is a 2 input AND gate to the library when it has something like this it will have a leakage power unit it will have a cell leakage power and it will have a state leakage power. Now, there all the states are not given. Now, let us say for the total time of 600 it can be re-unit now set in a big we are able to tell you by some way that this the state A into B that means, A and B both being 1 happens for 33 percent of the time. So, the 60 percent of the time is for other states right. So, what what is the weighted average is 0.33 into 0.2 because 0.2 is the leakage power when the state is beyond B and we are telling the tool at 33 percent of the time that the this gate is in this state. So, 0.33 into 0.2 and that is the remaining remaining time is 0.67 into the default value that is the cell leakage power right. This way the tool calculates the leakage power for a particular gate. So, again the priority is the state dependent leakage power if that is the option it will take the cell leakage power if you can cell leakage power is option it will be fully deployed cell leakage power at B so, that is the attribute right, deployed cell leakage power cell leakage power and the state dependent leakage power again please note leakage power does not depend on the switching. switching, it although depends on the state of the signal. So, for a state dependent leakage if the state of A and B is 1 the power is different, if the state of A and B is something else the power is different right it can be state dependent, but not switching dependent. Now, a very important so, I was stressing on the fact that leakage power depends on the B 2 on the threshold voltage of the device. So, you could have cells with low V t, but they are faster, you could have cells that are high V 2, but they are slow. So, static power dissipation has an except exponential dependence, it is not even linear. So, it is a it is exponential dependence on the switching frequency of the promise reporting, in order to address the needs of the low power IC design, the technology library provider provide cells with multiple threshold voltage. So, now, already we saw that let us write down the whether 2 input voltage, now that 2 input voltage will probably come in towards the threshold level right. So, what we what is popularly done nowadays is that, there are now 3 threshold voltages for each cell that means, the 2 input non gate which will be available in a low V t flavor, a standard V t flavor and a high V t flavor. The high V t would be slowest and best suited for power, the standard V t will have a standard delay that means, between high and low V t power is also between high and low V t, the low V t would be fastest, but the least. Now, how do we use, how do we as a designer use this thing or how does power compiler as a as an easy to use these cells. So, what is what is clear is that, for all low speed application or when the clock frequency is lower or let us say the path is easier to move, it is logical that we should use the high V t power, why? Because even if the cells are slower, since we are working on low frequency or a large time in path, the high V t should be able to meet the time, but it will be consuming least power, least least power right that makes sense. Again for timing critical path, you can implementally try and replace high V t by standard V t, if the time does not, if the time does not meet, you will probably go to low V t. So, for a typical of a big block, a typical cell distribution should look like this, the high V t would be about I say 80 percent of the cell would be high V t, because similar number of paths would be either easily met or all those taking to know, about maybe 15 to 17 percent would be standard V t and very few cells, may be 3 percent, 5 percent or even lower than 1, even 1 percent would be low V t, because low V t would only be used in very very time in critical path, very highly time in critical path right. So, many for many people to use that, they will they will say that ok I will only use high V t to be best to achieve best power number, I will only synthesize with high V t and since the critical paths can change after synthesis right, synthesis does not have the accurate net information, because the design has not been placed and routed right. Since synthesis does not have the accurate power with the net number, the capacitance numbers, the accurate information is available only after place and out of the model. So, the critical paths can change after place in the model, they do change in the process. So, what I can do one method of the I can apply that I synthesize with high V t, but I enable standard and low V t only after placing out of the model. What it does to my design is that, my design is majorly high V t and only let us say real critical paths, real critical path will be appear after all this, only the real critical path have either standard or low V t. What this gives me is a design that is optimize the model and optimize for time right. So, there are again many many ways by which you can achieve this whatever I dispense just one of the way which I have been using in this industry or you would see that power compiler in fact, how this power compiler do that right. So, power compiler can automatically do that for you, how does it does right, we will see in the upcoming slides. So, but it is very clear that present day needs, present day technology library has sets of multiple V t which would support multiple V t and you should use them and the tool you should use them to achieve good power numbers right. So, this was so, what we discussed in the last two slides was the power calculation for the static power, for the leakage power. Now, we will let us look at the dynamic power or the internal power right. Now, when computing internal power this power compiler. So, first for leakage power the attribute for the leakage power, for dynamic power the attribute is called internal power that is why I have written internal power right. We do not confuse it with the short circuit power. Now, this here the internal power is the attribute that library is used to denote the dynamic power right. So, when computing internal power power analysis will use the information characterize in the logic library. So, now this is sorry sorry this internal power in fact, refers to the short circuit power within the cell. So, we will see the dynamic power that is based on the switching of the output load capacitor within the service line. So, this internal power in fact, represents the switching power but totally internal to the cell right, internal to the cell, but counting the capacitor that is implicitly built into the gate at the output right. So, the output is connected to the and the combined range. So, that capacitance is also included right plus the short circuit current. So, here the internal power refers to the power that is completely internal to a cell which includes the short circuit power plus the internal capacitance, but not the load capacitance extra load that is applied to the not the fan output right. So, when computing internal power it uses the information characterize in the logic library the attribute is called internal power. The internal power table is very similar to the the timing table cell right cell fault table. Again for non-linear the most popular model is the non-linear linear delay format, non-linear delay model LNDM it is very similar to the timing table right. So, both have look of table base and both can be multi dimensional. So, in case it is one dimensional the the the constrained input is the input transmission. If it is two dimensional it could be input transmission and output load capacitance. It can also be three dimensional it is not popular though input transmission output load capacitance for two outputs that have equal and opposite logic only like q 1, q 1 power q 2 or q 1. So, there is a look of table. So, power is calculated on the actual factors one is the weighted average input transmission time that is the output load capacitance. Here the output load is the implicit load that is on the output of the gate not the load presented by the next right there is the internal power. So, it is very similar to timing you can open up the library and see the internal power attribute just like it computes timing power compiler computes the power numbers for dynamic power interface right. Again this is stated particle now cells will often consume different amounts of internal power depending on bits input transmission right. Let us say let us say there is a complex terminal the inputs are a, b, c and d the output is there, but now when we go inside this standard cell we see that there are three levels of logic this is how it is built let us assume this is how it is built. Now, when we input a transmission three and gates are affected, but when input gate transitions only z is affected what it means is that this case the standard cell has different power numbers for different cases. So, again this is stated part dependent. So, power compiler will choose the appropriate part dependent internal power table for an output by checking the related pin attribute. So, timing is also has a related pin attribute power also has a related pin attribute. So, what what timing in power tables will look like for this cell? The pin z for related pin a there will be a power table and a time table. Again for d it will be different in both a and b. So, power compiler does not choose the worst power number. Now, this is dependent switching please note this this kind of power is dependent on switching. Assume that power compiler knows how a and b even b are switching. So, whenever d switch it it will take power with respect to d. When a switch is it is going to take power number from a table with for which the related pin is a right and so on right. So, it is always stated part dependent. Now, let us talk about the switching power. Switching power is the power that is can be used in the charging in this channel in the local. This is not the internal power this is power that is due to the switching of the cell, but switching on and off of the load capacitor connected. So, this load what what does this load come from? This load comes from the net right. Again we understand that in design compiler the net information to remove it it is not accurate. So, this kind of power again is in a string because the load itself is in a string. So, PC is equal to VGT square by 2 P load into TRI which is the toggle rate PC is the switching power of the design toggle rate is the toggle rate of the net I transitions per second VGT is the supply voltage right. So, we saw that a signal that transitions for let us say once per cycle the alpha value is 1 by 2. So, we we substitute the value of 1 by 2 here and we we substitute the the switching by the toggle rate which is transitions per second. So, this formula is same as the earlier formula not different. So, the number P is equal to VGT square by 2 submission of. So, VGT is constant submission of submission of P load into the toggle mode. So, each net load into how many times it stop is we add them together multi-cliar VGT square by 2 this is how we get the switching power right. This can be either if we are working at the pre layout state that means we are working in a synthesis data base synthesis message it will be an estimate. We can also we can also use power compiler we can read the capacitance information the accurate capacitance information after the layout has been done it is called a force layer data base we can also do we can also this is the process called data notation when we read the capacitance from a separate file and applied on to. So, what design what what what netlist has has information on the grid and the number of nets. So, we can choose the force layer of netlist, but now for each of those nets in the netlist design compiler the power compiler also needs to be capacitance and everything. So, each of those nets this data comes from a separate file which is called the best square the most popular format is there SPA. This process of reading the capacitance from a from a separate file is called back annotation right. We will see a lot of back annotation in unit file if you do not understand it now we will we will see more details in the future it will be clear. What I mean to say is that accurate capacitance information can be type back into the power compiler for accurate power. Now, if we have been talking about switching a lot we have been saying that switching power becomes always through switching, but how do we give this information to power compiler? How does power compiler know we give it a netlist we give it a design which has 10,000 gates how does power compiler know that what gate switches how many times what gate switches how many times how does it know that this information can be provided to power compiler or it can be estimated this type of information is for switching activity right. So, the dynamic component usually accounts for a large obviously, the dynamic component is the largest part in the total power convention as compared to the static component internal power of cells and transitions from logic 0 to logic 1 and vice versa will directly affect the dynamic power of the design. This toggling of logic from one value to the other is called the switching activity right combined together we call it the switching activity. Now, how is switching activity model? Now, there are two very important factors of play here one is known as the static probability. So, static probability is the probability that a signal is either at a specific logic state. Now, please know that we understand that dynamic power is both state and power component. So, you should first know the power compiler should first know what state the signal is in right this affects both dynamic power plus it also affects the leakage power right because the state power again is also state business. So, it is expressed in the number between 0 and 1, SP 1 is the static probability that a signal is at logic 1. Similarly, SP 0 is a static probability that the signal is at logic 2. So, how the static probability is calculated? It is calculated as a ratio of time period for which the signal is at certain logic state related to the total simulation time. So, for example, if SP 1 is 0.7 it is known that a signal is at logic 1 state 70 percent of the time. We do not know we do not need to know that when the signal is 1 we only need to know let us say that total simulation time is 1000 nanoseconds. We do not need to know at which point the signal went to 1 or at which point the signal went to 0. We just need to know the total amount of time the signal stays at home right that is the only thing we want to know for static probability. Second important factor is known as a toggle rate. Toggle rate is a number of toggles a signal makes a net make from 0 to 1 and 1 to 2 a net spring or a port right. Again we do not need to know when it went to 1 or when it went to 2 we just need to know the form right the number of time it transitions in a given time is a toggle rate. So, toggle rate is usually per second basis. So, toggle rate could be another count divided by the total simulation time right. So, the file is called the file which has this information is called SAIFSF switching activity interchange format. So, the accuracy of the power calculation depend on the accuracy of switching activity. So, what is the best way to calculate this? As I was saying before put a particular design again let us take an SSM. We will in all of the cases we always have a stimulus a test bench static exercise a decimal for real-world cases. We take such test case we run it for let us say 1000 we run it for that we dump out the waveform using the VCD format for example. And now the VCD have all the information that we need right a VCD let us say we are running the simulation of a gateway right. Now at gate level for each of the net the VCD has information when that net occurs for each of the pin it has the information that how much time does it stay at 1 how much time does it stay at 0. What we now have to do is just convert this simulation data into the SAIF right. So, SAIFSF is an ASCII format supported by SNOPC to facilitate the intelligence of information between various analysis tools. We can use the command called read SAIF to read the SAIF file. We can use the command write SAIF write SAIFS is not the obviously, when you generate SAIF from simulation data you have to read it in the right is used for some other purpose use when we use an estimate we can write out those are using write the SAIF. So, the main the main purpose is that the main aim is to provide accurate to the information and for that we need a good stimulus right. Good good means a machine mode system a mode which is the makes the real work out right. So, we generate a simulation data. So, SAIFS generation can happen at multiple levels. First it can happen at RTA level what is captured synthesis invariant element what is synthesis invariant means all the registers would be captured right. The registers are synthesis invariant right or you have used any hard coded cells they will be captured they are synthesis invariant right. The invariant means they will not change after synthesis they will stay all registers inside always drop. Some will be optimized off obviously, but for SAIF person we can say that they will stay right. What is not captured internal nodes are not captured because there is no wait level data right. So, there are no internal nodes. Obviously, correlation of non synthesis invariant with man and women there will be a lot of combination logic which will get optimized off it is not captured switching is not captured right because it does not have accurate time information. State and part dependencies this optimization changes the state and part dependencies right. When we will optimize a combination logic you will change the number of nodes and hence you will change the state and part dependencies. What is a tradeoff you get a fast run time at the expense of some accuracy. So, the first level SAIF 5 can be generated from RDS simulation right. It will be very fast, but it will be least accurate. The second level can be. So, what you could do is you can do a first pass synthesis and now you can use that gate level net clear to generate a more accurate SAIF 5. You can do a zero delay or a unit delay simulation. Now, what is zero delay unit delay simulation or hope we will get to learn that in another course, but I will just summarize it. The simulation which is done without accurate gate delays which the unit delay or a zero delay assumes that each combination element has zero delay or unit delay or each sequential element has zero delay or unit delay. So, it does not have an accurate delay information. It assumes a deployed delay for every gate. This kind of simulation is again very fast compared to the accurate delay simulation, but the advantage is that what is captured is that it has all the synthesis elements right because it is a gate and a gate. It has internal nodes, it has part dependencies, it has state dependencies, that is the reason right. What is not captured some part dependency and this is this all of the extent the delays are not accurate they are just zero or unit. The glitching is not captured and obviously, after I mean some part dependency is not captured because some because again the delay is not accurate right. When the accurate delay comes into picture some transitions might change, some transitions might follow some other transitions. So, there will be some some state some part dependency which will not be captured, but but it is very very much much more accurate than how to use, but it has a significantly higher end time. When you go into the industry you will see that RTL simulations will run the fastest. Gate level simulation with unit delay will run slower. For example, in RTL simulation that runs in let us say popular power for a bit design, it will take probably a few more hours for gate level unit delay and for gate level with accurate delay information it might even take a couple of days right that is the. So, that the time simulation time increases exponentially with the number of elements, RTL has a least number of elements. Gate delay gate level net list has a lot more element than output. Again gate level with accurate gate delay again has lot more computation to be done right. So, full time in gate level what is captured everything, highest activity, the tradeoff is again the higher end mode right it has a lot more runtime right at ELM. So, what is the best tradeoff? You do first class synthesis you get a gate level, done a true simulation, there is sitting activity right that is the best tradeoff. This is the technical this is the flow chart. So, RTL design VCSMX is a simulation tool from synthesis, it can dump directly dump state for you right or you can run through simulation if you use any other tool you can dump a format for VCD. Then you if you use a you can use a utility called VCD to FTIF this is a gain forms and also suggest it will dump a SAS file for you. In any case you need a you need to design a SAS file. You can plug back this SAS file you can use a read SAS here inside design compiler power compiler and now based on the switching activity power compiler will give you the power number it will give you the this power number. You go through gate level design you can synthesize it either you can do it. So, you are since you are working in RTL you will have a sliding lesson activity that is why it is good for this part. It will give you the average power numbers again you will go through synthesis you will do some power optimization maybe. Then you will go to a power reporting tool and prime time PX is nothing, but again a tool which will report power for you. The SAS map is the name mapping which will report this SAS this SAS into since the name changes after synthesis. So, this utility will map the names of RTL to gate level at least so that this new SAS this name change SAS can be read inside prime time PX and you can analyze all. What we will see in this session we will see our scope is this one where we read the SAS in design compiler analyze power optimized right this is where we are focusing. This step is again very similar this step is not too different from this step. The only thing here is that time time PX you are using after synthesis you can even use design compiler power compiler the results are same the engine is same the software right. Now let us see let us see a safe example this is a safe example this is the SIF example. It tells what is the design name design name is instances TV popular instances TV when they short come for test points it tells what tools is used to write this. Now this instance TV contains two instances DOP and V12050 something like this for each of the nets this five tells us that so total simulation time is 99999 another second time scale is one another second each of these nets P0 is the amount of time that net pay that view P1 is the amount of time that net stay that at a logic one this is the amount of time that net stay that logic value PX. PC the toggle count is you can see the toggle count of each of the nets this is toggle count is 46 this net toggle count is 0. We can also see that it stays on 0 for 0 time that is why obviously the toggle count would be 0 it never transitions to 0 it all the time it stays at one this net again the or the T0 is 61 T1 is something T1 is the toggle count is again 26 again similar for so this instance here it tells us again T0 T1 value again it now tells us that it probably has inputs A and B so it tells us that condition A when A rise is what is the I think IG is the yeah so T it tells us what is the toggle count when in different conditions condition A rise or your path B condition A fall or your path B B rise B fall so it fixes one input it transitions other input it falls and then it tells us what is the toggle count right. So from this it says 5 so it will be easier to understand if there is 5 if you have a corresponding if you can take a look at the TV but I do not have that what you can do is you can experiment on your own you will probably know how to do gate simulation or gate level simulation take a small design take a small design run it for say a second and you can dump out the ACI in the game right. I will not have I will probably not have this I will not probably cover this in the now but it is very easy to do this I will see if I can find out an assay this file and read that and then cover this in one but I have to be sure about that, So now this is this point we know what what power number is what are the different types of power the static power the W power input and power switching. We know how power compiler reads this data from the standard cell library we also know how to get how to provide these switching activity information to power compiler. So now we have all the input data that we can give to the tools now how do we analyze power way. So it is very simple we from from in the gate level simulation or RTS simulation we generate a switching activity we give the technology rather the gate level like this. So apart over and above the setup that you do for design component for basic system like this you just need to have one thing which is switching right that is the only thing you have rest all things are same and what we do is we just do a report just like report timing or report area we do a report power. Report power has these many options we probably see few of those in the lab you can read again you can read you should read the man page this is the report power report. So it tells us that what is the global operating unit it tells us what are the units the leakage power unit is picked up directly from the library the dynamic power unit is derived from the EMT units. So this now tells what is the internal power breakdown the combinational power special power it tells us what is the count and other power I guess would be hard macro it tells us what is this internal power in the switching power it tells us the obviously total dynamic power in the form of internal power and switching power you can see that here the internal power is much more than the switching power right 76 percent is the internal power what this says is that this says it is probably a report just after since this is obviously the number of nets in a pre grade level design I am of left this captures the real capacitance will only come after 4th one right. So the switching power would increase in most of the cases after the layout is done the internal power would remain same why because internal power does not depend on system and will probably I mean I mean I think probably because the number of gate the number the lot of buffers and inverters will be set up the layout that will cause more power. So this is the pre layout power right the portion of power dynamic power or leakage power both will go because the number of cells number of nets both will go. It also tells us what is the leakage power so you see that for this particular design for this particular technology the dynamic power is much more than the cell leakage power. In fact the cell leakage power is kind of negligible but it is not so in the present technology the leakage power is very real threat in designs which are being done in 45 nanometer. It tells us the break breakdown also the estimated power the sorry the netlist power and the estimated clock three power again clock three power can only be estimated at this point because no layout has been done and not very sure how how it is able to estimate clock three power. I think it is just calculating the power of the buffers in the clock three there will be so many buffers that is why we see that it is a it is a lesser component right in terms of the total power. So we summarize total power is a sum of leakage power and dynamic power dynamic power is a sum of net switching power and cellular power. Now a good question would be I do not have any switching activity I have not done any solution I do not have any switching activity what do I do? So power compiler gives provide some default value so power compiler needs to only know how the inputs are switching right. Now each of those inputs it is it can know how all the internal nodes are switching right. So it uses something called P 1 it assumes it is 0.01 what it means is that for each of the input it will assume that the input stays at one only for 10 percent of the time this is the assumption this is the default value of the P 2. So there are two things to switching activity one is the static probability we are talking about other thing is the toggle rate. So for static probability it assumes to be 0.1 10 percent static probability for the signal staying at logit level toggle rate it assumes the toggle rate to be 0.1 into fclp that means for each data signal it assumes that the toggle rate is 0.1 into the block frequency which is specific to that network specific to the data signal not the maximum frequency although there is option by which you can control you can say that okay assume that all the network is maximum frequency. So fck fck is the frequency of the input selected block the command to apply these things is for its net switching activity you can use the command to give the give the default activity values. So using the defaults for static probability and toggle rate can be available for data rest but it might be unacceptable for some other signals like reset or a test signal. Now reset and test enable signal they will so a signal like reset will toggle very too much it will toggle once twice during the reset sequence and later it will be stable and DSL. Such kind of toggle rate values might not be good for the signal they should be careful about some signals which might be static for a long amount of time or some signals which might have a greater activity. So these defaults are otherwise good for maximum number of data. So default values these are the variables that define the default value power default static so again static probability toggle rate. So the variable is power default static probability or static probability power default toggle rate for toggle rate. Now you have a variable for power default toggle rate type which tells that the default is fastest clock that means by default our compiler will use the fast we will have multiple class we will use the fastest clock as the value of CLP. You can also change this by applying by using this command that system activity that you can look at the man pay NC and you can apply for each of the signal you can say that input input use a particular clock. So this was what you do when you do not have a switching activity between you can apply some default switching activity. So we have done this understanding the power terminologies we know now how to provide what to provide to power compiler to analyze power we saw the report power. Now let us come to some power optimizer input right. So now we know how to report power but we have to understand now how to optimize power right. So clock gating is I would say it is a most popular RTL or or gate level power optimizer input. Clock gating applies to synchronous load in a register which are the group of flip-flops that share the same clock. So we are talking about a group of a type of circuit which is very very frequent in your it is very popular type of circuit it is quite similar type of circuit. It is very very popular I mean Joe you are designed to have a number of shift wave which share the same clock and same synchronous control signal that are inferred from same HD variable. By synchronous control signals we mean it could be a synchronous load enable, synchronous set, synchronous these types of registers that are conceptually represented by a register with a feedback loop. So they have feedback loop in place. This feedback loop is activated on an enable signal right or the enable signal what we are talking about this is the synchronous control signal load enable if this feedback is enabled. So for some of the state this feedback would be enabled and the register the whole bank of a register will be entered with same model what it means is that a register band which maintain same value type it after typing the data there is not toggling but the clock is always toggling it consumes unnecessary power. Clocking saves power by eliminating unnecessary activity on the clock associated with reloading register band right. Sounds complex but it is very very simple when we look at the figure. So let us look at a register band this register band might have 10 register, 8 register, 16 register and any number but so it has it has multiple set blocks. Data out goes to a mass data and goes to a mass whenever enable is 1 load enable a data value is loaded here whenever enable is 0 this keeps on cycling with the same model right this enable would be generated from a control logic which is working on the same clock as the register band. So this is a very typical circuit that is a candidate for clock data you will not even realize it but this is how a lot of code there are lot of registers like this. So you have you have an on this clock you have an inside condition or any even have a new condition you say if enable some enable data gets new data otherwise data does not change does not change. So the if enable condition active is this one if en this en would probably be generated from a control logic working on the same clock. So lot of article code is like this which results into a shift register which has a feedback mechanism to play this is a perfect candidate for clock data. Now what the idea is that we want to quantify where it is not enable right enable is 0 we want to switch off this clock we want to make this clock 0 we do not want toggling on this clock this will save power this will save a dynamic clock not the linker clock. Now let us look at the modified circuit with the clock dating input this is for large based clock dating there is a type of clock dating which does not involve the after what is this what is this before even looking at this people let us focus on what is clock dating how we can switch off the clock. So we can very popular method is and find the clock with an enable signal. So clock handling between enable signal if the enable is 0 the output will be 0 if the enable is 1 the output will be 0. So this is called and type of clock dating you can have an all type of clock dating if the enable is 1 that output is always 1 where is the enable is 0 the output is nothing but the clock input ok. So clock combined with an enable signal both fed into an AND gate or an OR gate will result into some kind of clock dating. Now AND gate it is popular for the clock the type where the active clock has is there is the positive S figure what it means is that if the clock is high. So the enable signal should not toggle identity enable switch signal should not toggle when the clock is high what it means is that if the enable signal toggles and clock is high let us say it goes from 1 to 0 right the clock edge will be clicked off you do not want that. So for such type of AND dating without latch when you do not use a lab you can put it on paper you see that without using a latch the AND gate and OR gate both now the enable signal is sweet to toggle at any time right. So you have lot more restrictions on enable the enable signal if the toggle during unnecessary time the clock edge can get clicked off we do not want now we do not want now that is why we use a now. So for a particular type of clock dating we use a particular type of latch now let us look at the figure now in this case the clocks are positive S figure and now we want to use an AND type of data. So this is where the dating takes place this is the dating setting. So enable signal AND clock are gated to provide an AND clock now the MUX as the data input is removed the enable signal instead of going to a MUX goes to a latch the clock goes to a latch now let us latch is faster and will be falling edge latch is the opposite polarity of the flip clock. Now what it what it does is that so here we have waveforms of clock and clock avoid. Now let us say enable toggles when clock is off. If enable toggles when clock is on this latch does not pass this value because this latch is closed when clock is high when clock is low this latch is transparent. So ENL value will get updated after clock falls sometime after that. So this is the trigger event for ENL pricing right the value of EN gets passed on to ENL. Now ENL is gated is handed with the clock. So now since clock is low ENL is low next high edge comes here right this is the trigger form what it tells us that that whenever EN goes high if the clock is high there is no effect the next clock edge will be transferred. If the latch was not there assume the latch is not there EN will directly go to ENL what this will do it will create a false edge here it will create a half edge here this would be the waveform and you do not want that you want the full width of the clock cycle of the hyper really want the full hyper not the half over or 10 percent hyper. So latch will prevent this so latch this this is the actual getting circuit then I will get the latch simply make sure that EN does not transition when clock is high right. So that is the edge is not clear clock and it provides a stable full pulse of the clock whenever there is an enable. So this circuit it does two things first it gates of the clock when it is not enabled it is same the functionality is same in this data if this register bank gets the same data whenever enable is through here this data is stable when enable is through because there is no clock the data is stable there is no problem here. Further the second thing that latch does it it keeps as a very stable circuit to avoid glitches on the clock right. So latch is to avoid glitch and gate is to actually gate the clock what is the drawback it adds one latch and one and gate it gets it gets rid of the mark. So it adds let us say one latch extra assuming mark is equivalent to an gate in terms of area it would add one latch per register path. So it results into an increase in area but gives us a lot more advantage in terms of clock right and if you have bigger register bank so you have one latch per register bank if you have bigger lot of bigger register bank the area growth is negligible but the power saving is equal to dynamic power saving. So it is a very important power saving technique and in my like number of years in the industry I have used it every single time right. So how do we insert this type of clock gating two methods we saw gate clock option in compile ectra it does not. So compile ectra minus gate clock will add clock gating so you do not need to read through the RTL right. So compile ectra minus gate clock will add this in the in the either the RTL or you can even add it in the netlist using compile ectra minus gate clock. We can read the netlist already it is a compile ectra minus gate clock in compile ectra we will do that. There is one more command for insert clock gating but it only does that at the RTL stage right. So the preferable command to use is compile ectra minus gate clock all the both both of them do the same thing but insert clock gating cannot do it on in existing synthesized design right. Now there are lot of clock gating styles so the the the diagram we saw was the was the clock gating style for positive edge trigger logic right. The style used was latch plus an angle. So there are a lot of styles like that of clock gating styles or the the command to specify this style is called set clock gating style. If we do not apply any style these are the default settings that we will use. So these are options that go along with the set clock gating style command. Sequential side type is latch minimum bit width for a register bank. So this three what it means is that any register bank which is so it is not useful to add clock gating for shallow register bank that means it let the register bank is only two registers right. So you will add one latch for two registers the area entries will be very significant. So you want to exclude all registers which are less than some threshold you can you can play with the threshold you can play with the number then see how much is the clock gating person how many clock gate what is the area entries you can do some external but default value is three that means for all register banks now that register bank should follow some guidelines right should have a particular kind of that is a feedback loop and so on right and then enable condition and so on. So all such register banks which meet the criteria wider than three, wider than including three will be candidate for clock gating system. Let us not go into set a constant hold constant we will talk about this later in this slide. Positive edge logic is AND that means for positive edge trigger set up it will be the one type of gating for negative edge trigger logic it will use another type of gating. You can draw it on paper why AND gate is suitable for positive edge trigger why OR gate is suitable for negative edge trigger right you can it is very easy to use. Control point control signals are related to DFT because you want in when you want to type the design for number of things that means in scan mode all the classes should be transparent so you have a control point and a control signal name again observation point and observation logic depth are related to form. Maximum turnout number of stages one sharing means that do you want to share this to update with any other register phone it is false by default it is false. Now let us talk about integrated clock gating what it means is that this is the most popular form of clock gating we have discussed clock gating but now almost all technology library can work what they do is that they make so what they do is they will create one standard cell out of this latch plus AND gate. So, there will be only one standard cell internally which has a latch in an AND gate and it will have the inputs like clock enable and output right and some inputs and outputs are standard. This type of cell is called ICG integrated clock gating set right that is what we are talking about here. So, how do we use that this is the most popular form of inserting clock gates that means back applying it integrated clock gating set. So, how do we do that we say that set clock gating style we tell so there will be multiple ICG multiple integrated clock gating cells one will be for clock gating logic one will be for regular gating logic. So, we tell design compiler that or power compiler set clock gating style what kind of cell I want to use for positive S trigger logic what kind of cell I want to use for negative S trigger logic this is one example of this command set clock gating style minus positive logic integrated this is the library name and this is the cell name. So, we can be a telling by this command by issuing this command we are telling power compiler that for clock gating for positive S trigger logic from the library integrated use myself right for clock gating sets also in the library there will be multiple tries available. So, you can choose any type and that cell will be upsized or down maybe later to solve the DRC solutions right. So, this is the way this is the clock gating this is the way you can use compile ultra minus gate clock to insert clock gating before that report in compile ultra minus gate clock use the set clock gating style command to tell design compiler that use this particular type of logic cell for clock gating. You can also use a command called after this you can use a command called report clock gating these are two different report clock gating command one is the summary one is the verbose report. So, this is a very interesting statistic that it will tell. So, it tells us that for for this for particular design number of gate it registers at 66.67% that means ok this has only 4 and we only 6 and let us look at a slightly more of it will have a detail, but we have what we will do is in the lab we will insert a clock with the clock gating design and see what is the percentage of it. In my experience for bigger design I have seen about 80% of the registers which quality for clock gating what it means is that in a bigger design it can happen that about 80% of the registers fall in the category of chip registers with feedback. It is a very very common circuit you can you can see that you can in your code you will not even know it may be a chip register with a enable pin which controls the feedback. So, this is why clock gating is becoming so popular it gets so much gain in terms of power gain and the area increases not that much. So, what it tells the report clock gating it tells us what is how many number of clock gating elements is added it added only one number of gated registers is 4, number of ungated registers is 2, total number of registers is 6. On the right hand side the report is more verbose it tells us that there are 3 clock gatings clock gatings which conform to clock gating style one what is that style sequential cell is latched minimum bit to the school I am not sure what enhancement bit with me positive this is the integrated cell that is using from the label. Negative as logic is odd control point is report control signal is a scan enable it is related to DSP let us not go into that number of stages is 2. These are the clock gates so it tells older there are 3 clock gates these are the 3 clock gates that is inserted this is the summary again very similar to the left hand side summary. So, it tells us that 100 percent of register by gating in the lab we will also see we will see report clock gating we will use an extra minute state clock we will also look at the net list look at the clock gating structure it will become much more clear if it is not clear now. You should also try this in the lab now the last step. So, now now in this last section you are focusing on the power of the addition technique. So, one thing you should do always is use the clock gating option if your lab is supports an integrated clock gating even if your lab does not support an integrated clock gating. Now, you know that any positive restricted logic the clock gating cells a good clock gating cell would be a lab that is an hand gating cell. You can without using an integrated clock gating cell you can tell DC that by using such clock gating style that. So, without if you are not using ICT DC will add a latch in an hand gated cell. So, it is not necessary to use ICT you can choose not to use it and then DC will add a latch in an hand gated by itself to separate cells from the standard level. But first thing you should check in a library if the ICT is available if the ICT is available please use that it gives lot more advantage later in the field later when you want to do anything you want to set some social constraints or you want to do any optimization separate optimization the presence of ICT will help a lot because now you have a what particular type of cell you know that this is a cell that is used for clock gating and you can use some script integral scripts to extract those on those cells and do things on it right. So, it always helps to use ICT the first principle which is always look into the library and choose and see if the ICT is available right. Now, second now this was a very particular technique a very special technique to save bandwidth power which we can do as part of compiler right. Now, let us look at the other power optimization things available inside DC we have seen this flow where we provide libraries, Netflix and option switching activity when I say option I mean that you can also choose to use the site switching activity come on to set the depositing activity if you do not have a service right. Now, there are power options we will see what these options are and now DC will perform power optimization in addition to having an area optimization and you have a power optimized gate available. For leakage what power compiler could do power compiler with for leakage also for dynamic for both it is possible to do that power compiler with this power condition on path with positive timing slack. Enable power optimization does not change the cost priorities of paths it will just add no constraint. What it tells us that power can only be optimized whenever timing slack is available. So, a critical path with very fast frequency with no positive track it is not possible to do power optimization. Any power optimization will accept will try and replace after the power program and a slower cell will not help in case the power is critical. So, any critical path with fast frequency will restrict power optimization right. When the target libraries are when you have leakage power attributes available and when you have cells with multiple threshold voltages power compiler will use the library cells with appropriate threshold voltage to reduce the leakage power. For example, you have a IVT, a smaller VT and a OVT recovery, HVT, SVT and VT. What power compiler will do it will choose HVT cells for all the multiple power this will reduce the leakage power. For dynamic power optimization it needs the switching activity you can either provide SAIA or apply some default switching activity. Again for for dynamic power you know that same kind of let us say for HVT cells will have lower dynamic power as compared to a NVT cell. If the HVT so it will choose not even not in VT dependent of the leakage will become VT dependent, there will be some cells let us say some flavor of AND gate which will be which will eat up lower power lower dynamic power and compared to some other. For example, gate bits with higher capacitance at load will consume more switching power. So, there are number of gates available you have all the switching power information available. Now what DC will do it will try and optimize dynamic power by using gates which have low load on the on the output to reduce the switching activity. What this will do is that it will slow down the power again right. Now let us say you have many let us say you have a 4 input NAND gate. Now a 4 input NAND gate might be very good for multiple stages of 4 input NAND gate that is a three stages. So, you will compare a 4 input NAND gate with let us say 3 stages of 2 input NAND gate or let us say 2 stages of 2 input NAND gate. So, a 4 input NAND gate will probably be better in area, but it will eat up more power. So, what DC will try to do is it will replace that multi input gate heavy gate by a multi-stage gate. What this will do it will make the path slower, but it will slow down. If it makes the path slower this cannot be applied on the critical activity right. So, and it obviously if the switching activity is accurate it will help DC to analyze taken 5 input input input. So, a dynamic power optimization requires switching activity bottom line again bottom line it will only happen for non critical tasks. So, how do the annotated switching activity we say we need SAIS and we can annotated switching activity or if we do not have SAIS we can use set switching activity command to set the values default functions right. How do enable power optimization of power optimization to work best the library should support multi input cell especially for leakage power yeah. So, so sorry there are these two side of two side. So, so enable leakage and dynamic power optimization we have to use these we can use these command before compile please know before compile you have to do that that leakage optimization to through set dynamic optimization to through by default and we are saying they are set to follow what it means is that by default compile will not do any power optimization unless you include set the variables to 2 right. So, this is actually the summary part for power optimization to work best especially for leakage power the library should support multi input cell. If your library does not have any multi input cell if you elaborate all all the for all the cells there is only one DT type which can you only have standard DT it is not much useful for power optimization and design company does not have any choice. So, there is no use in practice even enabling power optimization the results will not be much different. So, to use the power of leakage power optimization you should have multi input cell. So, any good library or these sub-micron technology will have cells with different DT cells right. I will check if our the library they are using all multi input cell it is not then we cannot do many things in the lab right. Chips for handmade applications they save power for now there are techniques this is these are very basic techniques reduce power that means using high DT for non critical power using clock rating. But consider a smart phone now a smart phone consider a very complex chip that is the brain behind the smart phone. So, what components it will have it will have a basement processor it will have an application processor. So, application processor is usually what we see in this specification as you know the power port or dual port system. So, this is the application processor there will be again a baseband which will decode the test the signal the GSM signal or the CD signal. Then there will be a lot of cores which will do different job one core will do the job of media processing which will probably have a separate GPU for more one core will do the audio processing one will be a touchscreen controller for it. So, there will be there are so many components in the smart phone very complex device there are so many components doing so many different job. Now, consider that you are talking on phone when you are talking on phone the video processor part is not playing any role. So, what such complex chip try to do chip try to do is that they implement different voltage on what they do is different parts of the chip works on different voltages even if they are working on same voltage they have different supply. So, that one part can be switched off when not in use this takes a lot of power. What if your video encoder or video decoder is on even when you are talking on phone unnecessarily power is being consumed. These types of flows are called low power design flows synopsis UPF is one such flow unified power format is one such flow which which helps us in in implementing these types of types of chips. It is a this the understanding the explanation of this flow is outside the scope of this course. So, I am not we not detail that, but please understand that I want to stress on this time that we understand that block gating, dk power optimization dynamic power optimization all these techniques are basic power optimization techniques that you can use for a single voltage design right. So, whatever designs you do in the lab with your lab will be single voltage line you can go back to design compiler it is half the power compiler feature available to you. You can see your library you can first understand the first assignment is look at the library understand how the power members are recommended. Second try and insert clock gating you do not have to do anything special in your RTS just use the use the set clock gating side and compile in the grid block these two things. Third thing use the these two switches to enable the leakage in dynamic power optimization by setting the default switching activity. See the report power reports next step would be in one of your simulation what we must be doing for my simulation in some design you are near the course dump out the VCD generate an SAIS repack the SAIS in the line compiler report power report power you should do all these things to understand the concept of it right. Thank you.