 We're going to start by looking at the synchronous bus protocol. To begin with, I've got a timing diagram for a synchronous read operation. This is one where a device like the CPU is going to request that say an IO device provided with some information. So it will put out a request on the bus for some piece of information. The IO device will go find that information and put it on the bus for the CPU to use. Our timing diagram has a lot of the elements that you'd expect. We've got a clock cycle, we've got our address and our control. We also have our data. We're going to read these from left to right. That will represent how time flows. So our clock cycle begins over here on the left and it ends here on the right. Our clock signal has one bit in it and it changes from high to low during the cycle. Most of the other information on our bus is going to have more than one bit. And we're actually not really concerned with whether those bits are zero or one, we'll just be concerned with the fact that they are set to something useful. Exactly what they'll be set to will depend on the operation that we're doing, the device we're interacting with, and the data being sent. But we'll really just be concerned with the fact that at some point we can say that these are fixed to something useful. So at the beginning of our clock cycle, we'll start on the rising clock edge. And our CPU or master will place the address and the control information on the bus. That will start to propagate down the bus. The slave unit will see the request, go find the data that it needs, place it on the bus, and then it will travel back to the CPU. By the end of the cycle, the data will have gotten back to the CPU, and it can go ahead and write it to its registers to be in some later computation. So throughout the entire cycle, the address and control lines are set. They're initially set to whatever the CPU needs them to be, and they just stay that way throughout the entire clock cycle. The data, on the other hand, is a little different. It's initially in some unknown state. We're not actually interested in what that state is. We just know that it's not useful. Once we get halfway through the clock cycle, the slave device has produced the data, it's put it on the bus. And now it's in a useful state that the CPU could read. So this line down the middle indicates that we really don't have useful information on the bus at the moment. As always, there's something there, but it's just not useful for the computation that we're interested in. We're really interested in this data, and the slave device has not had a chance to place it on the bus yet.