 So, today we will look at one very important issues today that is direct tunneling current and you know then we will see that in order to overcome this problem we need to use what is called high K gate dielectric. So, in the last class we had seen that when you have this MOS transistor with the silicon oxide as gate dielectric when you start applying voltage even though you are well below the breakdown limit of the silicon oxide you can start conducting through silicon oxide and that we said is Fowler Nordheim tunneling right. And we also discovered that the Fowler Nordheim tunneling is essentially a function of electric field across the occur that is if you are to plot your electric field as a function of current density with current density in a log scale. You will see that initially there is very little current and then you know it will take off exponentially and hence you see this linear dependence in a log linear plot and this happens at about 5 mega volt per centimeter or so. And then I mean if you continue to increase the electric field eventually you will reach the breakdown as well and if you recall we said what is very crucial here is electric field across the oxide right and this E that we are plotting here is really electric field across oxide I mean if you want to be more precise you call it E ox which indicates what is the electric field across the oxide. What it essentially means is a following right if it is only dependent on electric field then if you were to sort of plot this as a function of gate voltage the current density and you would expect that you know if you see this kind of a behavior for 100 nanometer thick oxide let us say this is oxide thickness is 100 nanometer and at this voltage across 100 nanometer you are able to produce an electric field let us say which will give an equivalent current density of let us say 100 milli ampere per centimeter square. And if you recall what I had told you last time is that at about 10 mega volt per centimeter electric field you start seeing current density of the order of 100 milli ampere per centimeter square. Now if you go to a different oxide thinner oxide let us say 10 nanometer for example then what you would expect is that because oxide thickness is coming down to produce the same electric field and same currents I need to apply lower voltages correct. So all that will happen is that this curve will sort of translate as these along the voltage axis right in other words you may say that the curve will look something similar here this is for T ox is equal to 10 nanometer the shape will look almost similar right it is only the voltage translation. And if you have anything between 10 and 100 nanometer you will have series of curves which will lie somewhere in this area. And here again at this voltage you have an electric field of the order of 5 mega volt per centimeter that will this voltage will correspond to that electric field because oxide is thinner. And for a thicker oxide in order to produce the same electric field you need to go to much larger voltage correct I mean that is what you would expect and as you start scaling down instead of 10 you know if you come down to 5 nanometer you know you would expect that you know this should again continue to sort of look like this that is what the follow non-diameter length theory says. Now what happens really is that as we scale start scaling this further and further 5 nanometer and below even at 5 nanometer you start seeing some departure from this expectation. And more particularly let us consider a case of 4 nanometer right let us say I have a 4 nanometer based on follow non-diameter theory let us say I need to get the current which looks like this let us say this is for T ox is equal to 4 nanometer. But very interestingly what happens is that you may see this behavior at very large electric field but meaning corresponding to larger voltage it but as you start scaling the voltage rather than current going down like this you will see that the current will actually tend to look like this. There is a huge shoulder in other words even at lower voltages which corresponds to electric fields of less than 5 mega volt per centimeter could be 4 mega volt 3 mega volt 1 mega volt per centimeter. You see significantly large leakage current and this let us say 4 nanometer in 3 nanometer you may say something like this you know this could be even more serious. So, in other words you start seeing a departure right from f n theory for oxide thickness in the range of less than 5 nanometer and this is especially at low electric field and this phenomenon is what we call direct tunneling current. Now, let us try to understand what is really happening here and if you look remember the follow not I am tunneling theory what we had said is that you have an MOI structure which is a thick gate oxide here and this is your silicon right you apply voltage the bands are bent and these electrons need to tunnel through into the oxide. But at lower gate voltages you do not see that as you start increasing the gate voltages this band bending starts looking like this and that is when you start seeing this toiling current. Now, let us imagine a situation right let us say this situation is for an oxide which is as thick as 100 nanometer or let us say even 10 nanometer. Now let us imagine a situation where my oxide is not as thick it is only 5 nanometer in other words it would or let us say 4 nanometer whatever it is then it will look something like this correct this is where you have your oxide boundary and this is where you have your gate electrode. Now you see what is happening here this distance is now comparable to the tunneling distance which would have any way happened due to the follow not I am theory right this tunneling distance is less than 5 nanometer you start seeing electrons going into the other side. Now the fact that the oxide to begin with itself is less than 5 nanometer even when you have a very low electric fields electric fields are indicative of this band bending low electric fields. But there is this gate electrode and there are these empty states and these electrons can easily tunnel through the allowed energy state and get collected in the anode that you have at the gate this is positive voltage and this is negative voltage right. So, as this distance starts coming down instead of 5 nanometer let us say I have just 1 nanometer thick in 1 nanometer thick this problem is even more severe because even when you have very low electric field for very low gate voltage the tunneling distance from substrate silicon into the gate electrode because gate electrode is right here now that is extremely small that is 1 nanometer. So, you will see a huge tunneling current. So, as a result of that the direct tunneling current is simply because of the fact that my gate oxide thickness itself is in the regime where carriers can easily tunnel through less than 5 nanometer. And in fact this tunneling is really called in remember Fowler-Nordheim tunneling we said tunneling through a triangular barrier because when the carriers were tunneling the barrier looked like a triangular barrier whereas direct tunneling is really you know so called tunneling through trapezoidal barrier accordingly there is you know slight difference in tunneling current expression. And there are very well developed models again you know you have an exact expression analytical expression which gives you the tunneling current in direct tunneling current regime. Let us not really look at that equation but let us try to conceptually understand that direct tunneling is a very severe problem when gate oxide thickness is less than 5 nanometer. And so much so that even at the operating gate voltages you know 1 volt or even less than a volt 0.5 volt you can have a huge tunneling current going through the gate oxide and that is what we call a direct tunneling current. And that is why you see a departure from Fowler-Nordheim tunneling theory as per FN tunneling you should not have had any current but because of the direct tunneling you have huge current. Now as you start increasing the field eventually if you have a very high electric field this barrier again starts bending very severely. And you may again approach a case where the tunneling is happening through a triangular barrier not very high electric field. At that point you know your tunneling current will be as predicted by your Fowler-Nordheim tunneling current. That is why at large electric field it may agree with the prediction but at a lower electric field and lower gate voltage it will completely depart from the FN prediction. So, this is the problem with the direct leakage current you know in other words direct leakage current direct tunneling current can happen at gate voltages as low as 1 volt or less. You see 1 volt is the operating voltage of a transistor what it means is that if I have this transistor let us say N channel transistor I have applied 1 volt which is the operating voltage of the transistor. And you have all these carriers electron sitting here they will easily tunnel through this and result in a very large leakage current through the gate oxide. So, this is a very serious issue it is very serious issue for two reasons right. Obviously it is a very serious issue because you increase your leakage power or so called standby power. When the chip is in standby state transistor is not switching you should not have any leakage right. But you know as you know in a circuit there is a steady state logic some gates are at 1 some gates are at 0 and so on and so forth. So, you can have very large leakage current. And not only that you can also have an impact on you know reliability such as for example noise margin especially if it is a you know memory device for example, you can leak your charge through this gate oxide tunneling which is not a very good thing right. So, these are very serious problems you know and typically you know the figure of merit that we would like to put you see is that when the transistor is off if it is a n channel or p channel remember when the transistor is off there is this so called sub threshold leakage current correct. That is also a leakage current in a transistor, but that leakage current is a current flowing from source to the drain correct. So, typical off state current or leakage current in transistor is really sub threshold current. One figure of merit to use when to decide when to use this oxide or when not to use this oxide is to say that my gate induced leakage current I can tolerate may be when it is about 10 percent of this conventional off state current. But if this gate induced leakage current starts becoming comparable to the sub threshold current then there is a another big leakage component for your transistor right. So, typically you do not want your gate current to be comparable to sub threshold in other words you really want I g to be as small compared to the sub threshold current. And your sub threshold current of course is your typical off state current in a transistor in a typical sub threshold current that we see in high performance technologies. In high performance technology what we mean here is that the technology or the transistors that are used to make a very high end microprocessor which need to be very fast transistor they also tend to have large leakage current. The typical off state sub threshold leakage current spec today for this kind of technology is of the order of 100 nano ampere per micrometer. Remember I had told you all the currents typically that is the on current and sub threshold off current of a transistor is always specified as current per unit width. What it means is that this per micrometer it means that if your width is 1 micrometer then your sub threshold off state current is 100 nano ampere. On the other hand if your width of the transistor is 10 micrometer then accordingly your leakage current will increase 10 times right. So, that will become you know 1000 nano ampere or 1 micro ampere. So, that is how we specify this. Now, when we talk of the gate leakage current the gate leakage current spec I g's instead of I g we give current density spec just as the off state current here we normalize with respect to width of the transistor because depending on what is your width you scale it with width right you get the appropriate on current and off current. The leakage current is going through the entire gate area and hence it makes more sense to give a specification in terms of current density. So, typical current density specifications again depends on what technology you are looking at. Let us say if it is a high performance technology again we can say that my j g current gate current density specification could be something like 1000 ampere per centimeter square. We you know the number looks huge, but you know it is per centimeter square. If you were to scale it to micrometer square correct you know you divided by 10 to the 8 correct 1 centimeter is 10 to the 4 micrometer and 1 centimeter square is 10 to the 8 micrometer square. So, this is also equal to you know 10 power 3 by 10 power 8 ampere per micrometer square correct right or you know what is it you know it is essentially 10 to the minus 5 ampere per micrometer square. So, that is the kind of current density that we are talking about. This is for a very high performance technology right and accordingly you know one can also convert this you know into an equivalent if you know what is the gate length of the transistor right. Then you can you know factor that in and you can convert it into appropriate spec which looks like ampere per micrometer if you wish right. For example, what I meant there is that let us say my length is you know specified let us say this is something that I am doing for a 20 nanometer kind of a technology. So, what is 20 nanometer 20 nanometer is 0.02 micrometer correct correct. So, what would happen essentially is that you know just to keep it simple let me make it 10. So, that you know I do not have to multiply with the factor of 2 right. So, your 100 nanometer is 0.1 micron and 10 nanometer is 0.01 micrometer correct. So, then what you can do is that you can say for this length of a transistor then you can specify this gate leakage current in terms of ampere per micrometer width. Then depending on what is your width because you are going to make this transistor with 10 nanometer length and your width could be variable depending on what is your width you multiply with that width and you get the total current density correct. So, in other words you can take this number and you know what will happen is that if I were to express this in terms of ampere per micrometer of width just as of my sub threshold current density current spec is also ampere per micrometer width of the transistor then it would essentially look something like this your g g will look like you know this is 10 to the minus 5 and this is 10 to the minus 2 10 to the minus 7 ampere per micrometer and you know what is it it is essentially about 100 nano ampere per micrometer because 10 to the minus 6 is 1 micro ampere. So, this is 100 nano ampere per micrometer. So, what I try to do with all this round about calculation is that the reason why we chose 1000 ampere per centimeter square is that given a transistor of certain width and let us say length of the order of 10 to 20 nanometer your leakage through the gate is becoming comparable to your conventional leakage because of the sub threshold conduction right. Now, that is a problem because there used to be only one conduction mechanism leakage conduction mechanism sub threshold. Now, there is a gate leakage beyond this I do not want to really have any more leakage because then your off state leakage is just not governed by your sub threshold leakage your off state leakage is governed by your gate oxide leakage that is the worst thing to happen. And that is how we come up with the specs like this you know 1000 ampere per centimeter square or the same thing can be expressed as as I said 10 to the minus 5 ampere per micrometer square right these are the different ways of doing the same specification or you could call the same specification as for a length which is well defined you know this will translate into something like 100 nano ampere per micrometer width of the transistor right. But the crux of the matter here is that gate leakage direct gate leakage is a serious problem at the operating voltage of the transistor unless we do something you know we will have a huge problem in terms of controlling this and that is what is shown here right. What this is telling you here is that you know as we scale down the technology right decreasing the gate length we have to decrease the oxide thickness and this is how a typical 65 nanometer technology or as 90 nanometer technology will look this is a transmission electron micrograph showing silicon ultra thin silicon oxide which is of the order of 1.5 nanometer and a gate electrode. And if you shrink the length further you need to shrink this further and that is when there is a huge leakage current tunneling current and quantum mechanical tunneling current for T ox less than 5 nanometer starts happening which is called direct tunneling current. Tunneling current is an exponentially dependent on oxide thickness a very small decrease in oxide thickness results in a huge leakage and this results in static power dissipation as well as various other problems that we talked about. If you do business as usual you know we will have to scale oxide thickness silicon oxide thickness less than a nanometer you see sometimes we fail to understand the magnitude at this length scales. What is nanometer? Nanometer is 10 angstrom 1 layer of silicon oxide is 5 angstrom it is as if you have only 2 layers of silicon oxide that is it that is how thin it is your silicon 1 layer of silicon oxide another layer of silicon oxide even if 1 layer is missing in some region it is a deviation of 50 percent you cannot tolerate that and that is where we said if I decrease it further there is no way I can build chips. So, what do you do? You need to think of something else and that is the concept of what is called high K gate dielectrics it is a very simple idea if you think about it. We are building transistors by growing silicon oxide on silicon why did we scale silicon oxide? Because we were scaling gate length the drain was coming closer to the source if you recall drain induced barrier lowering on all those effect the gate electrode should also be brought very close to the channel otherwise you lose gate control in other words I need to enhance field effect from the gate. Now, what is the field effect due to? The field effect in an FET is due to capacitive coupling correct your gate voltage that you are applying here will capacitively couple to the channel the very reason why we wanted to decrease oxide thickness is to enhance that coupling capacitance that in turn enhances the field effect. Now, this is what we did we wanted to enhance capacitive coupling the easiest way for us to do was decrease oxide thickness because you do not need to worry about anything else grow the oxide for shorter time you get thinner oxide, but then we hit a road block the road block is this you cannot decrease oxide thickness any further if you do that you have a huge current going through this. Then we discovered look the capacitance equation has another term here and do not worry about area typically we look at per unit area capacitance epsilon is a constant we cannot do much about epsilon naught free space permittivity epsilon r is a relative permittivity and this is what we also call as k epsilon r or k are the symbols that are used interchangeably. And we said look I need to increase capacitance as device physics dictates because drain is coming closer to source I need to have more capacitive coupling, but why do you want to decrease t ox necessarily why do not you keep t ox varieties or even increase t ox to suppress leakage current and you choose a different material all together which has large k value what is k of epsilon s i o 2 s i o 2 epsilon r is approximately 4 3.9 to be precise, but let us say 4 round it off to 4 that is your relative permittivity and what we are saying is a following instead of silicon oxide which has epsilon r of 4 let us choose an imaginary material which is an insulator and that has a k value or epsilon r value 40. Then we are saying if this is a case rather than using 1 nanometer of s i o 2 if you were to use this whatever k thickness which is 10 nanometer they are equivalent equivalent in the sense they produce same capacitance, capacitive coupling here and here is exactly same. So, that is a very interesting observation and what it means is that as soon as you increase this to 10 nanometer what is 10 nanometer 10 nanometer is the distance between let us say your cathode here and the anode electrons are trying to go from cathode to anode because these 2 electrodes came so close to each other less than 5 nanometer there is so much huge leakage current why not increase the distance. So, if you increase the distance direct tunneling is suppressed all together and you still do not lose in device physics in terms of building a good transistor threshold voltage control because you have same capacitance coupling and hence the name high k gate dielectric it is a gate dielectric and it is replacing silicon oxide with some other new material and this is what is illustrated here and in this context we use a term called EOT and EOT you know essentially means that you know rather than this I will give you a this is expressing total capacitance right if you go back to per unit area capacitance what we are saying here is that let me so we define a term called EOT or it is essentially called equivalent oxide thickness it is defined as t high k I will just say h k or t k k indicates it is a high k material times epsilon r of silicon oxide which is you know 4 let us or 3.9 or let me just say k of S i O 2 divided by k of that high k material this is how we define the so called EOT what EOT means is that even though I have used a thicker material it is equivalent of using a silicon oxide of this thickness in other words if I use a 10 nanometer material insulator which has a k value as I mentioned of 40 then it is equivalent of using 1 nanometer S i O 2 that is the meaning of EOT in literature if you see recent literature you see this term quite often EOT of 1 nanometer or we have achieved EOT of sub 1 nanometer using hafnium oxide gate dielectric it does not mean that the physical thickness of hafnium oxide is 1 nanometer or 0.8 nanometer it just means that it is equivalent to using silicon oxide of 1 nanometer but in fact I use the hafnium oxide which may be 5 nanometer or 8 nanometer depending on what is its k value and that is the concept of this EOT this is a very important concept to remember. So, that is why we need a high k gate dielectric now what high k gate dielectric you know the huge possibilities is there a basis in choosing this all these are some examples of high k gate dielectrics right these for example silicon oxide is our conventional gate dielectric. So, what are the additional properties that we are looking at in high k gate dielectric dielectric constant is one thing we want to go to a thicker I mean higher k value. So, that I can use thicker insulating material but band gap is also an equally important property not just band gap we also say band offset is an important property. So, what we mean by that essentially is so let us say what are the requirements one is of course k is greater than 3.9 that is very obvious otherwise we cannot make the film thicker. The next one is that large band gap and along with large band gap we also need it is not just sufficient to just have large band gap, but large band offset for conduction and valence band both this is a important requirement. Then we need to have a excellent interface what is this interface silicon and high k interface remember we said the reason why silicon technology is so successful is that we can build excellent FETs in silicon because silicon oxide silicon combination is you know got given right gives an excellent properties at the interface in terms of surface passivation. Now, can I get the same surface passivation using this new material instead of having 10 to the 10 per centimeter square interface traps if you have two orders of magnitude higher traps then you know you are throwing all the advantage of having high k because your mobility will be so low and your threshold voltage could be so high that you can never build a transistor. So, that is an important aspect then stability we sometime call it thermodynamic stability thermodynamic stability what we mean by this is a following remember after you do your gate oxide you do various other processes you see and those are all high temperature processes you may have gotten a very good high k material, but subsequently can it withstand all other high temperature processes or whether it starts disintegrating right. So, that is a very important consideration and then if you can do all this then you know ease of processing how do you process it I mean are there process techniques available to put this high k dielectric on top of silicon because in case of silicon oxide it was very easy expose silicon to high temperature to oxygen ambient you get silicon oxide, but how complex are these new processes and then of course one last, but not the least is reliability. Remember we talked about the time dependent dielectric breakdown and all that you have made a high k dielectric with all these properties, but is it going to sustain the operating electric field over 1 year 10 year or what have you you need to meet all these requirements only then you can build you can replace silicon oxide with high k gate dielectric. You may be surprised that the research on high k gate dielectric is at least 3 decades old people have been looking at alternate materials to replace silicon oxide for last 30 years and it is very recently just about 5 years ago that we were successfully able to replace silicon oxide with hafnium oxide. Now most of the state of the art manufacturing technology all the chips that are made are not made on silicon oxide dielectric gate dielectric they are made with hafnium oxide gate dielectric. Why did it take 3 decades to get to this point because of all these conflicting requirements may be able to satisfy one, but may not be able to satisfy others. So, why do you need large band gap it is very obvious right the band gap when we are talking of band gap what we are saying here is that you have silicon which is 1.1 e v and let us say I build n channel transistor with poly silicon gate the n plus poly silicon gate will have a Fermi level here and this is a p type silicon which will have a Fermi level below the intrinsic level. Now you need to interpose an insulator here right if this insulator were to have a very very low band gap remember this offset is important because that will determine what is your tunneling current let alone direct tunneling even following what I am tunneling remember of course direct tunneling may not be there because we are making a thicker film because k is large you see, but if this offset is small the following I am tunneling has a one very important factor in exponential term that is barrier height. And in silicon oxide I have a barrier height of 3 electron volt here for electrons about 4 electron volt for holes. So, what we are saying is that we need to have a new material which has a reasonable band gap also band offset I do not want all band offset to appear for electrons and no band offset to appear for holes that is not good it is good for n channel transistor electrons cannot tunnel, but your p channel transistor holes can easily tunnel through you see. So, that is why we say not just large band gap, but also reasonable band offset. In other words if you are looking at two situation where in both have same band gap let us say this is one case this is some band gap x and there is another material which gives the same band gap, but this material has quite a good band offset, but both electron and holes whereas this material has good offset for electron, but it is very crappy for holes. So, your p channel will not work so that is why we had this two requirements going together large band gap along with that band offset for conduction and valence band. Excellent interface is obvious because these are the interface states you want to make sure that the interface states are as low as possible. Stability as I mentioned all the subsequent high temperature processes it should withstand ease of processing is obviously important in terms of manufacturability and reliability is also very important. And this is why you know if you look at some candidates I will illustrate that to through may be this example here. Look at T I O 2 very nice k 80 to 170 high k, but band offset for electrons is good band gap is good reasonably good, but band offset for electrons is 0. That is in other words what it means is that for T I O 2 if you have silicon here if you make a T I O 2 on top of silicon then T I O 2 will look something like this T I O 2 has a band gap of 3 electron volt, but it has 0 band offset with respect to conduction band of the silicon. That is not a good thing that as I said you need to have a band offset for conduction band band offset for valence band. So, in spite of the fact that it has such a high k it is of you know no use really for us whereas silicon nitride it has nice band gap good band offset for both electrons and holes are not listed the valence band offset, but k is marginally higher than oxide. So, that is why we did not really spend too much effort in silicon nitride because even if you go there may be after another two generation you will have to replace silicon nitride again. Most of the metal oxides these are all metal oxides have reasonable k values depending on which oxides that you are look at you know aluminum oxide of the order of 10, hafnium oxide anywhere between 15 to 30, zirconium oxide 12 to 16 the variation depends on how did you prepare that oxide it could be varying depending on that condition. There are class of oxide called rare earth oxides is represented as R E O 2, rare earths family is in periodic table if you recall such as erbium oxide or gadolinium oxide right all these are essentially your rare earth oxides. So, there are lot of candidates. So, one has to really look at all the requirements and as I already mentioned today this is already being used in sub 65 nanometer technology we are already using hafnium oxide gate dielectric only then we are able to get E O T of less than 1 nanometer I could not have use silicon oxide less than 1 nanometer because I am doing this you see what is this essentially telling you is the following right this is a calendar year this is taken from I T R S roadmap that we talked about in one of the and this year you know what you have here is called J G limit J G here is given as ampere per centimeter square I told you that 1 e 10 to the 3 is 1000 ampere per centimeter square that is what we discussed a while ago 1 e 0 3 now you know the J G limit could be different depending on which technology you are looking at older generation technology may have more stringent newer generation technology because your sub threshold leakage itself is increasing you can afford to have little more gate leakage current also. So, what this is showing here is a J G limit how it is being altered over generations for different kinds of technology this is called bulk technology this is you know now what is also plotted here is that this here transition point what it is telling you is that in a bulk CMOS technology as I am going along the calendar year I am shrinking my gate length and hence I have to shrink my gate oxide that is when the gate leakage is increasing exponentially and when the gate leakage hits this limit beyond that I cannot use silicon oxide meaning of this graph and that is when it says high k needed beyond this crossover point that is when you must replace this silicon oxide with the high k gate dielectric right. So, it is the same thing that is depicted in a slightly different fashion here now what is shown here is a very interesting graph based on various data reported in the literature on x axis I have physical thickness EOT in case of silicon oxide it is really physical thickness, but in case of high k it is an EOT value. So, this what I am plotting here is EOT if you continue to use silicon oxide as I decrease gate oxide thickness this current increases exponentially and you know go over this is 100 ampere per centimeter square this is 1000 ampere per centimeter square you are above the leakage spec when I go to different materials right such as hafnium oxide is here zirconium oxide here, prosidium oxide, aluminum oxide this is from various groups in literature, but in all these cases for the same EOT you are able to bring down the leakage current at any given point that is the idea. So, I am still at the same EOT as if I am using Si O 2 of that thickness, but I can have may be few orders of magnitude lower leakage current, because I am using a new insulator well it is not clear whether hafnium oxide which we are using now is scalable you know in the next 5 to 10 years, because in the next 5 to 10 years we may have to reach a EOT of 0.1 nanometer less than 0.5 nanometer that is very very thin EOT value. The problem is two fold right, because whenever you try to put an high k on top of silicon invariably you end up having a very thin silicon oxide either intentionally or unintentionally sometimes intentionally, because if you have a very thin silicon oxide you get a very nice interface remember silicon oxide has that excellent property of minimizing the traps right as we have discussed right. So, that can happen intentionally by growing it less than a nanometer kind of a thing or unintentionally sometime, because sometimes you may have a interfacial reaction subsequently if it is not very stable during high temperature processes. The metal oxide in general some M O 2 can react with silicon and can give Si O 2 and M or it could also form silicon which is not a good thing right. So, there is a practical problem especially to get for EOT less than 0.5 nanometer can we do that I think jury is still out there I mean we do not know that we will have to wait and see what could happen or whether there are alternate materials you see there is lot of efforts that are still ongoing you know especially there are these so called rare earth materials such as lanthanum oxide which is illustrated here you know what is shown here is that this is so called Gibbs free energy of formation what it means is that it just indicates how stable is this oxide for subsequent thermal processing. The lower the better the lower this is more stable it is it would not react with the silicon to form interfacial layer and some of these rare earth metal oxides also have reasonable band gap. There is a lot of work going on oxides such as lanthanum oxides, erbium oxide, gadolinium oxide to see whether these oxide can replace hafnium oxide in the next few years. But this is a very interesting evolving area at present we do not know what will happen later. In the context of high k gate dielectric I may also bring up towards the end of this lecture now next 5 minutes or so that there is another place where high k gate dielectrics are in required those are to build dynamic random access memories. If you have studied DRAMs at some point in time DRAM is a simplest memory cell that you can imagine all that we have is at every memory cell memory cell you know is a two dimensional array of pixels at each pixel we have a control transistor and a storage node or a C storage this is also called DRAM capacitor. This is what typically is called your world line of the memory and this is what is called a bit line of your memory correct your memory is essentially a two dimensional array of world lines and bit lines bit line is where you read out the data world line is where you apply the control signal to read a particular bit from the memory array. So, the way it would work is that this is the most compact memory cell you can ever imagine although in the recent days there are few very interesting memories that are emerging to replace and to miniaturize the memories further in future. But currently if you have to compare DRAMs static RAMs and flash memories DRAMs are the most compact that is why your you know storage the highest storage that you have in computers apart from the hard disk is essentially DRAMs because you can build very high density memory using DRAMs. You store a charge here and whether you have stored a charge or not stored the charge that is your logic 1 and logic 0. When you store a charge this charge should not leak out if you have stored one, but in DRAMs there is this problem of leakage leakage is either due to sub threshold leakage now it becomes very clear for you. Otherwise you might ask if I apply a 0 why should the trial charge leak, but there is always a sub threshold leakage current you see and that can leak the charge and similarly you can have junction leakage and so on and so forth. And that is why in DRAMs there is something called refreshing whenever you read a data from DRAM you should also refresh that you rewrite that and even if you do not read the data you will have to refresh it quite often. You need to minimize the refresh time you need to minimize refresh cycles. The way to do that is to store as much charge as possible and hence I need to have as large capacitance as possible and capacitance being epsilon naught epsilon r a by t. You can certainly scale t, but you cannot scale t very significantly, because again you have leakage current in addition to this transistor leakage current you can have a dielectric leakage current just like any dielectric you have fallen or I am tunneling and direct leakage tunneling. And leakage current specs in DRAMs are several orders magnitude stringent compared to leakage current specs through gate oxide capacitor in high performance transistor. For example, the DRAM leakage current spec through this capacitor is of the order of 10 to the minus 8 ampere per centimeter square compared and contrast this with the gate oxide leakage current spec of 1000 ampere per centimeter square that we are talking about. So, here the problem is even more severe I really need to make sure that I make it really thick reasonably thick so that my leakage current is well within the spec and hence if I need very large capacitance I need even higher k values. Whereas hafnium oxide with k of 15, 16, 20 may be ok for your transistor for DRAM you may need k of 50 100. So, again in DRAM you need high k such that your DRAM high k should be much much higher typically than your transistor gate high gate oxide or gate dielectric high k value. Because the leakage current spec here is very very stringent compared to the leakage current spec here, but there is also one saving grace here although it is more stringent in terms of the leakage current specification. Remember that when you build a DRAM capacitor we are not really necessarily looking at any interface with silicon because this is a completely different beast here there is no current flowing under this capacitor. Whereas here under this gate oxide capacitor there is a current flowing from source to the drain and hence you also need to have an extremely good mobility here extremely good interface at least that is not a very serious constraint here and that is why typically the DRAM capacitors high k capacitors are what we call MIM capacitor which is metal insulator and metal capacitor. As opposed to the transistor which is MIS capacitor which is metal insulator and silicon or semiconductor in general, but in this case silicon both are high k material in one case it happens to be part of a transistor and hence you have metal insulator and silicon. Whereas here you have metal insulator and metal because it is only a capacitor to do high k dielectric and storage and that is why you know here various other materials are really being looked at such as for example you know TiO 2 and some material called BST which stands for barium strontium titanate all these are huge k values like 100, 150 whereas here I do not need to go to 100, 150 you know beyond certain limit there is no need to increase k value in a transistor structure that is another very important point that I want to bring up here. If you are looking at transistor structure what is the advantage of using a very high k I can make it very thick you see is not it if the k is low I have to make it much thinner. So, if you have a very high k you remember this is a huge k value then in a very short channel transistor less than 100 nanometer or so remember we talked about drain induced barrier lowering that drain electric field coupling directly to the source similarly when you have a high k material here and huge opening so to speak you can really have what is called fringe induced barrier lowering what it means is that there is a fringing field and that fringing field can start becoming more and more powerful as your k value starts increasing more and more. So, the message is the following we need to first recognize why are we increasing the k in the very first place in the very first place we are increasing k remember 3.9 k is silicon oxide silicon oxide as a high leakage current here this is the point by increasing k value you can make thicker insulator, but as soon as you reach a thickness of 5 nanometer or so your direct tunneling current is just suppressed completely beyond that increasing the thickness has absolutely no value for you. In other words if you were to look at this decrease in leakage current what happens is that it just gets spec here at some k value which corresponds to a thickness of 5 nanometer or more if you increase the k value and increase the thickness beyond 5 nanometer you do not see any benefit. On the other hand what could happen if you look at your sub threshold leakage now let us say I have some sub threshold leakage if I start increasing the k unnecessarily you do not gain in terms of any further reduction, but you may actually lose in terms of your sub threshold leakage starting to increase why could this happen this could happen due to so called fringing field induced barrier lowering. So, the message is that in transistor it does not help you to go beyond a certain k value just do whatever is required for you what is it that why you are why are you doing it you are doing it to make jg 0 once you get jg 0 do not over do it if you over do it you will essentially undo all the advantages. On the other hand for memories DRAMs it helps you to get as high k value as possible because we are not really talking of a transistor structure there it is only an MIM structure. So, let me then summarize direct tunneling is a serious issue in today's technology unless we replace the silicon oxide with high k gate dielectrics we cannot build transistors today and we have successfully done it below 65 nanometer regime, hathnium oxide has successfully been used, but it is not clear whether we can continue to use hathnium oxide in the next 5 to 10 years there may be other candidates as well DRAMs also require high k gate dielectrics. So, we will stop the lecture here.