 Hello, and welcome to this presentation of the STM32 Low Power Universal Asynchronous Receiver Transmitter Interface. It covers the main features of this interface, which is widely used for serial communications. The Low Power Universal Synchronous Asynchronous Receiver provides full UART communications at 9600 baud when the LPU art is clocked using a low speed external 32.768 kHz oscillator named LSE. Higher bowed rates can be reached when it's clocked by clock sources different from the LSE clock. Applications can benefit from the easy and inexpensive connection between devices, requiring only a few pins. In addition, the LPU art peripheral is functional in low power modes. It comes with transmit and receive FIFOs with capability to transmit and receive in stop modes. The LPU art is a fully programmable serial interface with configurable features such as data length, parity that's automatically generated and checked, number of stop bits, data order, signal polarity for transmission and reception, and bowed rate generator. The LPU art can operate in FIFO mode and it comes with transmit and receive FIFOs. It supports RS232 and RS485 hardware flow control options. The LPU art supports dual clock domains allowing for wake up from stop modes and bowed rate programming independent of the peripheral clock. The multi-processor mode allows the LPU art to remain idle when not addressed. In addition to full duplex communication, it also supports single wire half duplex mode. The maximum bowed rate is 9600 bowed when the clock source is the LSE. 36 megabowd when LPU art cursey clock is 110 MHz. The STM32L5 devices embed a single LPU art instance. Compared to the use art, the LPU art doesn't support synchronous smart card, IRDA and LIN modes. It does not support the receiver timeout, modbus communication and the auto bowed rate detection features as well. This is the LPU art block diagram. The LPU art clock source, LPU art cursey K, can be selected from several sources. Peripheral clock named APB clock or P clock, SIS clock, high speed internal 16 MHz oscillator or HSI 16, low speed external oscillator or LSE. The LPU art clock source is divided by a programmable factor in the LPU art PSC register in range 1 to 256. TX and RX pins are used for data transmission and reception. NCTS and NRTS pins are used for RS232 hardware flow control. The driver-enabled pin or DE which is available on the same IO as NRTS is used in RS485 mode. The LPU art has a flexible clocking scheme. The registers are accessed through the APB bus and the kernel is clocked with LPU art cursey K, prescaled or not, which is independent from the APB clock. In order to pass data from one clock domain to the other one, either eight data FIFOs are used or single data buffers. The LPU art block is an APB slave that can rely on DMA requests to transfer data to or from memory buffers. The TX and RX pins functions can be swapped. This allows to work in the case of a cross-wired connection to another UART. The frame format consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error-checking. A frame starts with one start bit where the line is driven low for one bit period. This signals the start of a frame and is used for synchronization. The data length can be 9, 8 or 7 bits with the parity bit counted. Finally, one or two stop bits where the line is driven high indicate the end of the frame. The previous slide described a standard frame. This slide shows an example of an 8-bit data frame configured with one stop bit. An idle character is interpreted as an entire frame of ones. The number of ones will include the number of stop bits as well. A break character is interpreted as receiving all zeros for a frame period. At the end of the break frame, two stop bits are inserted. The LPUART supports full duplex communication where the TX and RX lines are respectively connected with the other interfaces RX and TX lines. The LPUART can also be configured for single wire half-duplex protocol where the TX and RX lines are internally connected. In this communication mode, only the TX pin is used for both transmission and reception. The TX pin is always released when no data is transmitted. Thus, it acts as a standard I.O. in idle or reception states. For this usage, the I.O. must be configured with the TX pin in alternate function open drain mode with an external pull-up resistor. In the RS232 standard, it's possible to control the serial data flow between two devices by using the N-CTS input and the NRTS input. These two lines allow the receiver and the transmitter to alert each other of their state. This slide shows how to connect two devices in this mode. The idea is to prevent dropped bytes or conflicts in case of half-duplex communication. Both signals are active low. For serial half-duplex communication protocols, like RS485, the master needs to generate a direction signal to control the transceiver, also called physical layer. This signal informs the physical layer if it must act in send or receive mode. In RS485 mode, a control line called driver enable is used to activate the external transceiver control. The DE control line shares the pin with NRTS. To simplify communication between multiple processors, the LPUART supports a special multiprocessor mode. In multiprocessor communication, it's desirable that only the intended message recipient should actively receive the message. The non-addressed devices may be put in mute mode using two methods, idle line or address mark. The LPUART can enter or exit from mute mode using one of two methods, idle line detection, address mark detection. The LPUART can operate in FIFO mode, which is enabled and disabled by software. It's disabled by default. The LPUART comes with a transmit FIFO called TXFIFO and a receive FIFO called RXFIFO, each being 8 data deep. The TXFIFO is 9 bits wide. The RXFIFO default width is 12 bits. This is due to the fact that the receiver does not only store the data in the FIFO, but also the error flags associated to each character, like parity error, noise error and framing error flags. Provided that the TXFIFO and the RXFIFO are clocked by the kernel clock, it is possible to transmit and receive data, even in stop mode. It's possible to configure TXFIFO and RXFIFO thresholds. This is mainly used to avoid underrun or overrun issue while waking up from stop mode. The LPUART is able to wake up the MCU from stop mode when the LPUART clock source is the HSI or LSE clock. The sources of wake up can be a specific wake up event, which is triggered by either a start bit or an address match or any received data. An RXNE interrupt when FIFO management is disabled or FIFO event interrupts when FIFO management is enabled. This table lists the LPUART events that can generate an interrupt. This table lists the FIFO events interrupts when the FIFO management is enabled. The DMA requests can be generated when receive buffer not empty or transmit buffer empty flags are set when FIFO management is disabled. The DMA requests can be generated when the transmit FIFO not full and receive FIFO not empty flags are set when FIFO management is enabled. Several error flags can also be generated by the LPUART as shown in the table. The overrun, parity and framing error flags are each set when the corresponding error occurs. The noise error flag is set when a noise is detected on the received frame's start bit. The LPUART peripheral is active in run, sleep and low power modes. The LPUART interrupts cause the device to exit sleep and low power sleep modes. The LPUART is able to wake up the MCU from stop zero and stop one modes when the LPUART clock is set to HSI or LSE. USART's reception is functional in stop mode and generates a wakeup interrupt on start, address match or received frame event. In standby and shutdown modes the peripheral is in power down and it must be re-initialized after exiting standby or shutdown mode. This is a list of peripherals related to the LPUART. Please refer to these peripheral trainings for more information if needed. General purpose input output, reset and clock controller, power controller, interrupts controller, direct memory access controller.