 So we're here at the Mobile World Congress and who are you? So I'm Gilles from Xalynx and welcome to the Xalynx meeting room where we have some very exciting stuff around our new RFSOC which is a chip integrating a lot of DAC ADC into it. So we'll start by some demonstration that we have on this side on the side with the RFSOC and we will end by demonstration that we have with barefoot networks and in-band telemetry that are very exciting. You call it the RFSOC? That's correct. Does it have to do with RF and the chip set? Yes, it's about integrating RF into a SOC chip that allows customers to remove a lot of the components and reduce the bump cost and the power in the 5G area. RF, is that analog? No, it's digital. It's digital to analog that we are integrating. So and you have the FPGA and the ARM and everything? We have FPGA, quad core ARM, we have the DAC ADC integrated into a single chip so that's never seen before. And that's very important for the mobile world? It's very important for antenna, like you want to do massive MIMO, bin forming. It's very important if you want to do broadband unit, so the baseband unit, sorry, and it's very important as well on the mobile backhaul if you want to play on this world as well. So it's end-to-end on the 5G network infrastructure. 5G is very important for the 5G? Yes. It's crucial to have this kind of stuff. It's crucial for the evolution and the integration that you need for the massive MIMO and the new antennas that you need for the 4.5G and 5G and as well crucial for the desegregation that's happening into the baseband unit and the mobile backhaul. Is it important also because the industry is moving so fast? You want to use FPGA technology because you want to update things more often and it's more flexible than designing an ASIC that specifically designs something. So everything is around the standards. 3GPP standards are evolving and will continue to evolve because 5G is not only the 5G wireless but it's also the NB IoT or the IoT and the connected cars and so the standards will continue to evolve and so the only way to keep up with the standards is to go FPGA and customers have asked us to integrate more so they can deliver higher bandwidth, lower latency into the antennas and into the rest of the network. In the past, is silence a big part of this market or is it a new thing for you? 4G was already a big portion, we were big already in the 4G market. Not with 3G? 3G was the previous market where the number of antennas required was not requiring the flexibility that you were talking about. So 4G already? 4G requiring a lot of new spectrums depending on the country, the radios were looking for different bands already on the 4G but this is accelerating with the 5G especially since this is not only customer flexibility that you are talking about but are looking for lower power and lower latency. And what does the ARM part of the SoC run? Is it Linux? It can run bare metal, it can run Linux, it can run accelerators or it can run algorithm as well that like you will see when people will do the demonstration. And is there this concept of an app store for networking? Is it going to be good for you? So it will be good for us but in fact we are looking for the application to consume the boundaries because this is what is pushing the massive MIMO antennas this is what is pushing the 5G to evolve customers want to consume more video, more AR, VR applications and this is what is pushing the network to evolve in the 5G. Alright, so what kind of demos do you have around here? So we will have the first demo and Anthony, Anthony you will be the first one up for the RF SoC so you can see what is the integration of the RF SoC into an SoC FPG means. So when was it announced? It was pre-announced last year and we are just making it public with the latest silicon level first time at Mobile World Congress. So where is this chipset? Anthony? Is it under this one? So what I am showing you right here is the characterization board for the RF SoC so on this board right now you take a look at by screen what we are doing is we are directly synthesizing we are directly synthesizing 5 carriers at band 42 that is 3.5 GHz going out into a ballon and we loop it back and we capture that carrier using our RF sampling ADC and we will mix that down to baseband and capture the information and we can take a look at this on the PC screen right here so if I just call up the GUI so this again is the signal that I am generating from the RF DAC again it is 5 by 20 MHz carriers centered at 3.5 GHz and then we use the ADC or RF sampling ADC to directly sample that signal and mix it down to baseband and here you can see the performance of the ADC it is a little hard to see right here but we can achieve an ACLR number approaching 54 dB carrier and the other thing to mention here is that we are about 12-13 dB full scale backed off on the ADC so very good performance for our RF sampling ADC So why is this important? Where is it going to go and what it is going to be used for? Well I think as Gils was saying earlier on we are seeing a massive increase in the number of channels being used in radios so one way to make that commercially viable is to integrate the RF DACs and ADC into the RF SoC so some of our devices will support up to 16 by 16 channels in a single device and allow you to get the power and the footprint down for these high order MIMO radios that are coming online for 5G Is this a development board? This is not a development board here this is a characterization board but we have development boards coming in the pipe and you will be able to prototype your radio on the development boards coming very soon It looks like there is a whole bunch of radios so what is this? Again these are simply just signal conditioning for the RF signals we have a differential RF signal we have a balance to convert it into a signal-landed signal I am doing a little bit of filtering and then it goes back into the ADC where we capture the signal again What is this over there? So this is a good question this is a spectrum analyzer from Roland Schwartz so this is one way for us to evaluate the performance of the DAC so we can look at the DAC output and see what is the party instrument like of this FSW and actually that is a good segue now we can show you the performance with the amplifiers attached that is actually what has been displayed here so we are actually the guys will show you a DPD in operation here on an 8x8 implementation So let's switch to the signal with the partner of Xalynx so Kevin will take you through the demonstration to show you how to use the RFSO and show you all the IPs that NanoSIM is developing and the value they are bringing Alright, so hi Hello, I'm Kevin from NanoSIM So what are you showing around here? So here we want to fully maximize the potential of this RFSOC device and we have actually developed if you look at this diagram we have actually developed a multi-channel wideband digital phonem Let me jump over here So this is actually integrated together with the RFSOC by maximizing the true potential of this FPGF fabric we actually developed 8-channels linearization solutions to it and in addition to that we have actually built and developed this front-end prototype and this prototype actually supports 8-channels MIMO system So currently the design is tuned to operate at a center frequency of 35-100 MHz that is precisely targeting the BAM42 applications So what are you looking down here? So here we have a characterization board and we fully maximize the capacity of the board by having by we fully maximizing the value of this evaluation board by utilizing our 8-channels of DAC and ADCs and each of them is running at the data rate of 491 MHz and this allows us to truly linearize the signals consist of for instance you see here it's a 2 5G component carrier where each is 100 MHz wide so the total signal bandwidth we're looking at is over 200 MHz All right So this configuration right here with all those cards is something you built? Yeah, this is a different example of one of the typical RF front-end module and this module consists of basically power amplifier suitable for wide band operation and for massive MIMO application and we have standard like anti-aliasing filter feeding into a gas 5V again high linearity driver that follows by a high power amplifier from NXP Cool and this is a swim swim we're starting from the RF SoC so and you have more demos? Yes, so let me introduce you to on-brows so on the RF SoC you remember I mentioned that we can use this part for the baseband unit or for the mobile back hole so on-brows will take you through the demonstration So this here is a right over here So this is an evaluation board for the RF SoC So this is an evaluation board for the RF SoC which has the 28 DR which has the SDFEC soft decision forward error correction block inside so there's A please in this chip this board we connected here to SDFEC SDFEC SDFEC this board we connected here to GUI where essentially what we're going to show in this demo is the following we have a data generator it goes through an encoder so we can get encoder statistics for throughput of an encoder we then modulate that signal and inject errors feedback through to a demodulator and then decode again and basically check the statistics and throughput of a decoder as well on the hard blocks that are encode so if you just jump to the GUI here you can see this is a performance demo where we have a dial for the encode and a dial for decode is essentially what we do is we choose our code for so 5G or Wi-Fi or whatever your code may be so we support LDPC turbo encoder and LDPC encoder decoder and turbo decoder so if I run this you'll see that basically now we can get up to 22 gigabits per second on the encode and 3 gigabits per second on the decode and then we also so it's pretty high this and we have a as I said there was 8 on a device so we can scale that to 8 soft decision forward error correction blocks, hard blocks that are not in PL so what I mean by that you actually have a specific hard block so this is the PL of the chip you have a hard block like an ASIC type block for just to perform decoding and decoding error connection is important in this kind of market so very important in that you're a channel as you're sending data through a channel it gets noise basically comes through the channel, come through the air come through cables etc so you need to be able to correct that error those errors so your final video or whatever is specific S&C just for that market exactly good, take side thank you and thank you and so let's go to the last one which is not purely related to the RFSOC but it's related to how to use FPGAs into the next generation networks which is the NFV applications where inbound telemetry is starting to be very important for the next generation network you need to collect more and more data to be able to process those data in order to be able to manage the networks so that's the next generation of NFV that we are showing live here and that Robert will take you through network functional virtualization network function virtualization is that also to do with the potentially app store for networking that's another story but virtualization is going to be important exactly because then you can really put the application wherever you want into the network and virtualization works great with the FPGA of silence as you have virtualization you need to have acceleration and then FPGAs or MPSOCs or FPGs with ARM processors can be very useful for that hello so this is an in-band network telemetry demo showing off this is an in-band telemetry demo showing off interoperability between three companies so we have over here an in-band tech switch powered by a barefoot tofino programmable data plane here we have an in-band tech switch with a barefoot tofino chip for the switch data plane and then over here we have two servers one running Xilin smartdix one for an int transit hop one for an int sync hop and at the top we have a server running barefoot deep inside so what we're doing here is we generate traffic we send it through the switch through various hops simulating a real world network and with the power of int we get real-time data about packets that are going through the switch we can keep track of things like ingress and egress time stamps queue occupancy hop latencies through the switch or through the smartnick for each individual packet the moment that is actually inside the switch and then at the end of the network we have an int sync node which will collect all of this data, pull it out of the packet and send it off to deep insight for analysis which will then show this to your network operators who can use this to analyze their network and make changes to their flows and deal with anomalies at a rise in various things so can you show one of these or is this or is this what's inside here this is what's inside so this is Xilinx this is the Xilinx programmable chip that's running our smartnick architecture we use p4 to program it so we have you can buy this yes people can buy this so what we have are two versions of this running inside of our network one one's running as an int transit node programmed with p4 to collect data about the packet path through the bnf and the second one is implementing an int sync which will pull out the data after the entire packet has exited the system we can achieve so this is like brand new this area right here yes so this is pulling together a lot of new technologies so p4 is a emerging language it's been around since 2014 but it had a recent update for 2016 and we're using that to program both of the switches is a spec that's currently being developed to determine which types of data would be interesting and how to format the packets as they're going through the switch and the smartnicks