 For this example, we're going to be working with this set of code. As before, we've got a dual-issue processor, so we'll be issuing two instructions every cycle. So I filled those in. We're just not going to worry about those too much. In our first cycle, we get an add immediate and a load word instruction. The add immediate will go off to ALU1, and I'll send the load word off to the memory unit. So our add immediate instruction is going to update T0. Our load instruction would also like to use that as its base address. So our add immediate instruction will be able to complete immediately and go off to the commit unit. But our load word instruction is going to have to wait for this data to be available before it can run. So it's not going to be able to run until cycle 4. Both of these instructions can be committed as soon as they reach the commit unit. Now I have load word and an add. Load word, of course, goes off to the memory unit. Add instruction, I'll send that to the second ALU. So our load word instruction is dependent on T0. T0 is available in cycle 3. So this instruction will be able to run in cycle 4, except that there's another instruction already using the hardware. So we'll wait until cycle 5, and then we'll be able to commit this result back in cycle 6. Our add instruction is dependent on A1 and T1. T1 was calculated up here in the load word instruction, so that's available in cycle 4. That means that we'll have to wait around until cycle 5 to actually run this instruction. Since there's still a slot in cycle 6 to commit a second instruction, we'll be able to commit this instruction immediately. Now we have an add and a store word instruction. I'll send the add to the first ALU and the store word to the memory unit. Our second add instruction is again dependent on A1, but this time T2. So we get T2 from our second load word instruction. So that will be available in cycle 5. Then we'll be able to run this instruction in cycle 6. Then we can commit this instruction in cycle 7. Our store word instruction depends on T0 and T1. T0 was updated way back in the add immediate instruction, so that's not a problem. But T1 was updated by our first add instruction. So we'll need to wait until at least cycle 6 to be able to use this data. Turns out our memory unit is free in cycle 6, so we'll go ahead and schedule that. And then since there's a free slot in cycle 7 to commit an instruction, we'll do that as well. Now I've got a store word and an add immediate. So I'll send the store word to the memory unit and the add immediate to ALU2. Our second store word depends on T0 again, as well as T2. T2 was calculated by our second add instruction. So that will be available to use after cycle 6, which means that we can do this computation in cycle 7. And then commit the results back in cycle 8. Then we just have the add immediate instruction. You know, it reaches our ALU in cycle 5. And we're going to use T0. T0 was updated way back here in cycle 3, so we can definitely just pull it out of a register and use it immediately. Update that in cycle 6. Our ALU is free in that cycle. So it would reach commit unit in cycle 6. And I can't commit it back in cycle 7. For one thing, both of my slots in cycle 7 are already full. For another, I have to be sure to wait until all previous instructions have been committed. So this instruction can also be committed in cycle 8. And that's how this set of 8 instructions would be processed by the hardware.