 we were looking for oscillators and pardon oscillator which is used in most of the circuits analog system as well as digital is a VCO shown here which is a tuning LCO oscillator and here the capacitor is essentially created out of a diode which is called vector because a variable capacitor with voltage or variable reactance or very cap the other word if you know a p-n junction depending on whether it is abrupt junction or it is linearly graded or exponential the reverse bias capacitance can be given by zero bias capacitance divided by 1 upon 1 plus Vr by 5b where 5b is the built-in voltage of the junction Vr is the reverse bias and m is the factor which is decided by the kind of junction I have for example abrupt junction is half graded is one-third it may vary from 0.35 to 0.5 depending on the grade you get get constant you get there typically in most cases 0.35 or one-third is true because the exponential function in a long range acts like more like a linearly grades but it is not 100% true because if it is a error function profile it may be slightly different Gaussian may even little different than exponential so please take it that values are normally provided by the technology people for their device if it is half then it is much easier to find 1 upon c square V is a straight line so the slope is the m factor okay so now with this in this case the diode the Vr essentially stands for the reverse bias 5b is the built-in potential which is for the given junction of source drain in the substrate that's the same diode I'll use that may have the typically 0.7 volt or 0.65 volt kind of built-in voltage and so I just have to vary the control voltage to get variation in capacitance and remember larger the voltage I apply smaller is the capacitance so the range up to which I can do is from the CJ0 to a lower capacitance that is higher frequencies so at the at CJ0 it has the lowest frequency and as I increase voltage the frequency will also increase because capacitance will decrease 1 upon 2 pi root LC so C decreases frequency increase of course for a too large a voltage breakdown may occur a normal PN junctions in a CMOS technology we have a breakdown of 6 to 10 volts beyond 5 volt normal devices do not permit more than 5 volts I can make diodes which are as they are called power rectifiers can stand 5,000 volts but this is not a power rectifier okay so it's a diode which is out of and normally even each PN junction is surrounded by an n plus region which is called guard ring which does not allow currents to spread out the reverse current okay so some other technology someday but this is what essentially and so it limits the breakdown for very low values so typical voltage which you can apply is 5, 6 volts and no more so the variation with this whatever is possible that's the maximum range tuning range which this CMOS technology will allow you for the VCO the little bit of maps be of interest which we already done but I repeat it again for the same clarity this is called mathematical model of VCO we know if I write a voltage V is equal to Vm sin omega t or cos omega t omega t has a unit of phase that's what it is omega t so one can say that d5 by dt is essentially omega rate change of phase is essentially the frequency or angular frequency so if I plot 5 versus t and if it is this kind of relation exist it will be a straight line that means the frequency is constant and corresponding to this you may have a sinusoid which may have a peak voltage of Vm here this is Vm sin omega t or cos omega t depends on where it starts at 0 or it started half way okay so this has a frequency decided by you can see the way it is the phi actually represents the frequency is that the phi t curve essentially represents the frequency pi 2 pi 3 pi 4 pi correspondingly d5 by dt is constant here so is sinusoid actually has the same frequency so you can see d5 by dt here 1 1 and 4 2 pi there will be one sinusoid and it repeats now if I have two signals V1 and V2 which have different frequencies omega 1 and omega 2 or has two phases phi 1 and pi 2 if you look at this just to prove what I made statement this has a higher d5 by dt or this has a higher phi 2 has a higher d5 by dt then pi 1 slope is higher there so if you can I can do the same thing here for pi 2 pi 3 pi for each such angle I figure out the frequency and you can see from here for d5 by dt higher this point is on the left compared to the lower one which means the frequency of d5 by d5 2 by dt will be larger you can see from here this moves has a larger frequency compared to this one so essentially slope of phi decides the frequency of operations this fact we actually utilize in PLLs that is what we do phase and frequency are related so if I can control phase then I can control frequency that is exactly what we are looking at so this figure this is this point clear to you what I said that if I have d5 by dt larger or smaller it essentially means the frequencies larger or smaller corresponding to it and that can be depicted if you have drawn this of course this is very trivial this you can always draw two lines put 5 pi 2 pi points and you can see the frequency here is lower compared to this which has because larger d5 by dt will have higher frequencies this is just to prove that point which I said and given in many books including Rojavi, Boyce Baker and everyone so the statement I am making d5 by dt omega is a valid statement okay and to therefore we can represent any phi t curve this is t curve into its equivalent omega curve okay so we say this is a slope then it has a frequency omega 2 higher slope it has a frequency higher than omega 2 which is omega 1 as long as this slope is maintained frequency is omega 2 let us say same phase same slope again occurs so you go down to omega 2 again it rises for the same slope then if it is different it will have a different frequency so this and this are essentially same so mathematically if I say d5 by dt is omega so integral of pi phi is equal to integral omega dt plus integration constant which is phi 0 which is called initial phase t is equal to 0 in a VCO we have done this expression earlier that omega out is omega 0 plus some constant of the VCO KVCO into V control this is the principle of VCO now we have a oscillator output which is say let us say given by Vm cos phi t so I represent cos phi from here in this expression okay so I get Vm capital Vm maybe you can take because I use small m again so if I write Vm cos integral omega out dt plus phi 0 so I now say the output voltage of a oscillator has this kind of representation is that clear if this is what you agree then this is what you should also agree okay why are we trying to do we want to figure out and this is very important that is why PLS are used in fact our worries are if let us say this control voltage which I am going to apply is not constant right now for example if I substitute this okay I think I made cos omega okay I will have to write now cos this omega out in here also so maybe I do that first so if I have this V capital M cos omega 0 KVCO integral V control dt plus phi 0 this is the expression I will get for V out if we control is constant then there is not much an issue okay but if this is not constant and noise over its so let us say generally the way it is expressed assuming right now phi 0 is 0 initial phase is 0 V control has Vm cos omega t as its voltage which is a CMOSI controller okay which may be overriding the DC value of V control. Now if that happens I substitute for V control Vm cos omega m t here in integral expand it integrate and expand it and leave some terms which are smaller so I get it is V capital M cos omega 0 t V 0 sin omega t KVCO Vm you can expand and get this kind of expression just put this integral here expand small term be neglected and you get this now if you see now I can further do little adjustment here and this can be then written as Vm cos omega t minus KVCO Vm Vm upon 2 omega m into this cos omega this is omega 0 plus omega m term and omega 0 minus omega m term okay if omega m is not present this whole time will go away and what you are expecting would be essentially see so control is constant you have a excellent oscillating frequency at omega 0 but if V control varies you have two other frequencies surrounding it which are called side bands these are essentially noise bands okay so some energy will be lost in side bands okay. So in many cases how do I retain control voltage constant or noise free that is essentially what we are saying we will do it through PLS is that clear so this whole issue of mass was shown to you that if there is a change in control voltage that reflects in side band power which is lost to you because remember if this is not present all the power would have spectrum would go to omega 0 if not part of the power will go on the side bands now this is very some in real life and one must actually see that your frequency does not change okay of course there is a word which of course when it comes I will talk to you later so is that clear why I am I am trying to see that why it should be some locking has to be done for the reference which I am creating and that is done through a system which is called phase locked loops okay of course they have many other features we will see one of few of them as far as this course is concerned this is good enough PLL may not be of course except for the bonus part of some small queries no mathematical theory because a huge area I can actually spend please 6 hours to 8 when 9 hours only on PLL designs by the most of the Indian so-called startup or industries in Bangalore Hyderabad Noida essentially are making PLLs of different varieties different IPs they create that their major bread and butter so do not think PLL is very trivial okay PLL is very very strong chip which so many people need at different applications so is that point clear that there is a sideband power loss if control voltage is not retained constitute so I start with phase locked loops as I say for most of you people may not be aware but this was invented as early as 1930 so it is not a very new thing or something phase lock loop was the word was known and even circuits were made as early as 1930 however the first digital first IC PLL came in 65 and first digital PLL in which digital signal were locked appeared in 1970 by the same year 1970 even sinusoidal or analog PLL were observed or actually made and similar time there were another PLL was used in optical signals and they were called optical PLLs so it is not just electrical signal phase lock loop does not have to do about electrical signal any signal you somehow phase it back adjust it you get it called PLL locking okay so these are something where you can use it to lock the V is VCO frequency I want VCO to be console whatever frequency I am using that should be constant VCO may generate something but I want that frequency should be constant of my choice I decide what is my frequency using VCO and PLL I can actually synthesize I can increase the frequency or divide the frequencies so it is called frequency synthesizers and almost every mobile phone or every television or every other kinds of receiver pagers telephony optical transmissions everyone uses PLLs in one way or the other and I keep saying a small company called core actually have 80 IPs produced last year on PLL just take a small company of 24 people of which four of IITB students and they produce 80 PLL chips as an IPs so you can see the business itself only for that company small company is on PLL so think don't think this is trivial this is very money-making system right now the typical definition of a PLL since I am not teaching this as a part I did not prepare heavily for every word of it as I say if you nearly need some maybe next semester make signal course you insist that they should teach you there if she or she who doesn't want to be there I will come and teach this is very important area for me I like this many of my students are developed is PLL so I will like to actually tell you how what's the problem PLL is essentially a feedback system that sort of a control that means it must have some feedback control it compares the output phase with the input phase please remember phase and frequencies are related is that clear so do not think that phase connection is this the comparison is performed by what we call as phase comparators FC up we will say phase detector first and that will compare as well so you call PD or FD FD is called frequency detectors P stand for phase detector and together we call PFD phase frequency detectors normally phase detectors are sufficient but much more accuracy and much longer range capturing if you want you may need a PFD that also can be a fully digital circuit which is called charge pump method some other day okay so phase comparator is essentially what we are looking for I suppose some of you are communication so you must be aware of these two terms but for micro electronic student it should not be Greek and Latin so let's see what is a jitter and what is a phase noise this is something which I always want to tell people there is a confusion and there is not a clear understanding between the two though they are similar if not same so please our major worry in all NLM designs are occurrence of jitter or equivalently saying occurrence of phase noise it is very difficult to handle these jitters or phase noise at very high frequencies and we are working these days on gigahertz is that correct we are working on gigahertz and at those frequencies this is very difficult to handle at lower frequencies this typically I might tell you there is a word which is common anything below 1 megahertz the change in frequency or change in phase is called drift and in if you are a my timer we used to call wonder wandering so now it has changed to drift but anything beyond 1 megahertz it is actually called jitter or phase noise depending on which way we explain it please remember even on the board if you have chips and interconnects PCB for example these two parameters as I say essentially similar but not same they are very important in board designs so not now remember the board design of 90s or 95 have become chip designs of 2000 plus okay now you are integrated more but the same issues which were occurring and the board has now come on silicon itself so the design issues are same as we earlier looked into board designs so let me tell you what exactly is these two words which comes into our mind jitter and phase noise I will not derive the expression for this how to derive one from the other look from some Google paper you will get it let us say we have a pulse of 100 megahertz and let us say duty cycle of 50 percent that is square wave so we believe that if it is 100 megahertz pulse the pulse period should be 10 picoseconds we believe that actually and it alternates at every 5 picoseconds it should come in every 5 picoseconds but this is only if you think you are right that is ideally it should happen that and if it does not the difference which is going to come is essentially called jitter so one I shown you this is your ideal pulse which you are expecting this is the period okay now what happens in actual transitions they can be early transition or they can be a late transition okay so the maximum early to late transition width in time is called jitter there is a early transition there is a late transition the maximum difference of early to late transition is called jitter okay ideally what should be jitter 0 I do not want any all transition to occur at 50 percent duty cycle if I fixed it okay at T by 2 but if it die on what is the range in which this can change the and any time change essentially we will say t plus delta t or t minus delta t which is equivalently saying in omega terms there will be a change in phase for that omega t plus something means time shift means phase shifts have occurred so jitter essentially gives you phase shifts those who are communication again they know much more about this but from micro electronic side few more words are important for both jitter and determine this phase noise if you have written on as I said these are I mean these are interesting part and I do not want to spend hell of a time on these but I wish I would have time enough to really teach you a PLL something you know in digital I like to teach memories for long same way here I want to teach PLL but somehow my course was so organized by me I know time left to PLLs and I was told by mixed signal people they do teach that so hopefully they will in case you take that is also a elective in case you need you can all other people all NL of people all digital people need a PLL come what me irrespective if it is only digital we say DLLs but DLLs also one other name called DL lock DL block so there is a difference there also please do not confuse with DPCR DPLL and DLLs some books do not differentiate okay is that okay or this is trivial so jitter is the maximum spread of time in which signal can shift from high to low or low to high is what we call as jitter there are two kinds of jitter seen one of course is deterministic the other is always the random one typical deterministic jitters are crosstalk two lines close by signal going across one can have mutual coupling between the two and depending on the direction of signal going it may have larger coupling or a smaller if they are opposite in direction there are larger coupling they are in same sense lower coupling forward crosstalk reverse crosstalk forward is easy comparative to maintain reverse crosstalks actually boosts the values too much and difficult to organize them of course then there are EMI electromagnetic radiations interference as the word goes this EMI radiations may come from the next line which is resonating at high frequencies or may come from other systems around in the block okay other chips can actually have this or in a dub of microprocessor or such thing other company including my power supply may actually emit EMI's EMS so if there is an EMI signal path we actually get into jitters and same way word is if not electromagnetic even the noise simple noise can be coupled between the two because of mutual couplings so there will be noise surrounding which may actually over read the EMI radiations coming from outside they are similar but different sources and finally there are two digital people are most worried that in a block of circuit you are lot many inverters are lot many days all of them switch one go okay out of eight let us say you acquired or eight eight in one and eight switch together they may lead to two major worries there we called power supply droop and ground bounds that is the leader will shift up power supply voltage may go down okay these are also essentially deterministic they may lead any change in anything will lead to jitters the other of course is random and in general if you are from micro electronics we always look into the upper part which we think we probably have some control if you are a communication plan he is very happy here or she is very happy here no control so she is very happy he or she is very happy random is essentially maybe because of the temperature maybe because of process variation maybe because of the interface states different interface states okay and since it is random most likely it follows Gaussian in nature Gaussian distribution it picks up and since there can be more than one jitter sources average value if you have to calculate is called RMS jitter please remember these are like a noise so noise is added up the same way this is also added up so jitter is something this of course deterministic jitters can be off drift whatever it comes we can offset it we can some compensation we know how much so we compensate partly for example if you want cross talk between any two interconnect line put a ground line okay space extra space but every signal line is surrounded by shield which is the ground line in normal cable you have shield on a chip there is no shield so you actually every alternate line is a ground line okay so only link between ground no signal on that that's how coupling could be minimized anyway at the cost of both size or silicon size the second part is phase noise which is as I say it's a related term but not same so if you have a variation in signal timings they can also be represented in frequency domains and normally they show a Gaussian distribution of this kind this is let's say iron oscillator whose power is shown here against frequency if there are no jitters or there is no noise all the power should have gone to the Taylor frequency which is my center frequency f not okay that that time oscillate will oscillate at that frequency so no issues fine everything but if there is a distribution like this as shown here some power is actually given to adjacent frequencies which results in sideman just now I showed you this same word shown here so now we define a phase noise out of this you can see what I do it at this frequency of whatever bands it has come at 0 plus f1 fm here I take a bandwidth of 1 hertz and figure out what is the power density and then integrate all the power which would have actually I got integration of total this power and ratio of the 2 is called phase noise is that figure drawn as I said this is not necessarily part of our course per cent design but good designers must be aware of everything this other than things do not work we do not know what to explain it may still not work but at least you should be happy it's not working because of this okay so that because word is how we know about okay and this spec is specifically normally given to we see how much phase noise available allowed so it's not that this is not a spec this is a spec so phase noise is defined as power in 1 hertz bandwidth of offset frequency that is 0 plus fm is the offset at that one 1 hertz bandwidth if you find the power there divided with total power of the carrier then it is called the phase noise and it's always expressed as db with reference to carrier divided by hertz dbc per hertz so we must actually design like an error if you are solving a chemical analysis what is the way we do it within this truncation error or what is the error bar we say okay truncate things so a pll be a particular error met top of the scope will take you what is the permissible phase error 5% 1% 0.5% you decide design okay that much time it will go through loop and will actually settle actually 0.5% sorry most permissible phase error is half percent now there is a circuit which is shown below which is more like a pll we have a summer here we have a low pass filter and we have and we want to have output frequency same as center frequency we see as output frequency should be the same as and there is a variation in input frequency from the center frequency so as soon as you that small delta T occurs this loop will operate and will bring center frequency to close to VCO frequency or rather opposite the VCO output will be exactly same as your reference output or frequency want even if jitter there are few other words which of interest to some this sigma part is essentially is what it does by a detector phase no no this delta T is in the omega form 0.5% that is at the phase for the center frequency whatever is the phase acceptable to use half that is let's say I have 1 mega half percent equivalent phase whatever is allowed their lock should stop let us say 1 mega half percent changes 0.99 megahertz 0.996 megahertz we don't want to go beyond further to make it 1 megahertz so it lock should stop there ideal it should be 0 it should lock exactly at that frequency but it may not because the components can never give 100% locks but that should be permissible for you jitter also give a little different statement there is a word which they say cycle to cycle jitter for example here it is D plus delta T when the next time it is T plus delta T to okay first of course is RMS value so average value of that is average RMS not average RMS value is normally taken for peak to peak or RMS two values of jitters are measured then there is called accumulated jitter over a given time after certain cycle how much is the net jitter occur to you it's called accumulated jitter for example here you can see now it is small small for a band this may be large enough a jitter and that may change your final phase itself okay so that is the accumulated jitter is also specified 5% okay of course then there is a jitter in duty cycle distortions 50% may become 49 51 that also can create more problems so these are essentially as I said terminologies in PLL books or PLL chapters if you read in a analog book as I said we are not going into huge detail of that some other day some other time for some other people okay so here is a phase detector part which essentially is shown here you have two signals V1 V2 which passes through a phase detector and create an output and the way we actually are looking right now is the phase difference which is delta phi and the average value of this V out should be linear now definition because this is one which is going to control the VCO frequency which is the control signal of VCO okay typical phase detector could be as simple as an XOR gate if you have two signals V1 V2 in the square form you can see at every this is an XOR so whenever they are not same values the output go one otherwise there are zeros since there is a jitter between these two at this frequency this is 0 but this is 1 so it rises it becomes 1 at this point again this is 0 but this is 1 so again against comes down so there is a pulse a small width pulses or markers come depending on this jitter you have and you will see once this kind of output voltage this then you take an average of this is that correct how do you take average filter okay so we will get only average value of that that value you feed it to be controlled and adjust your free is that okay the point is trivial but that is what I just copied from Rosary some other things this is of course is trivial as I said this is the DLL part essentially this only simple digital phase lock loop which is shown here okay there is also a problem of jitter in there is a jitter in signal and jitter in phase lock loop so we have a second loop the stability so there are issues and issues okay the four cases that I have discussed if between the two V1 V2 there is no change in phase so only at the you know for a very short duration transitions occur so the output also transits because this even if we say it is 0 it is not never 0 so it is marginal water so it gives markers how if it is pi by 2 as it is shown here 50 percent so for this time 0 but half the time there is one so you get an output of square wheels of this kind is that correct 50 percent of time you can see here this is one this is one so 0 but this is 0 and this part is 1 so wherever 1 0 occurs or 0 1 occurs XOR will give 1 okay so correspondingly you will get such purses and you should what actually have to do is the average of this okay is your control voltage integrator also can do the same okay then you have pi opposite phase opposite markers the transition wherever goes strongly negative we will show a mark on that if it is 3 pi by 2 it will give a different frequency part in this and you will get again pulses okay so depending on the skews you have you can always get the output and this output when average can change the VCO frequency and bring it back V2 and keep comparing between V1 and V2 so that finally they lock to a close by value up to one cycle yes one cycle phase range is this phase detection is possible and range is also clock locking is also possible more than 2 part it is second clock starts no no lock starts it does not pick up they should follow this model retongue model so before we quit PLL there are few interesting things about PLL which analog PLL use or analog signal processing people use is they inject a sinusoid signal into reference input which is the frequency at which you want the reference signal the internal oscillator means VCO lost the injected signal into reference that is what you want whatever this it should lock to that there is a frequency difference between reference and injected signal is proportional to the K of the VCO all right if it is locked it goes to 0 and internal sinusoid then represent the filtered version of the reference sinusoid and that is what you are looking at that you use as your output of a VCO is that clear x simple g-gmc filter case gmc oscillator k sath gm-gmc means what compensating the RP value okay yesterday I showed in a negative resistance this okay here is the PLL base PLL for a CMOS technology this is your VCO-gm was VCO yesterday I already discussed with you these are the diodes which essentially receives the control voltage this is that average RRC filter I just showed in a LPF this is that average RRC and this is your phase detector your reference input the frequency at which you want to lock the input this is your VCO you tune it to this close to this frequency feed it back compare it in the output here is locked to the reference or if you must have that there is no P channel device anywhere still called CMOS because technology CMOS the VCO is the control is coming from the phase detector averaged out so this essentially why I say PLLs are very crucial for real life requirements because you want to hold this frequency to a constant value before you use it into any particularly RF applications okay where is called image is very strong there and you will actually it will pass through the digital side and that may actually huge noise your capacitor requirement for a to D converter will be very large so it is very difficult to maintain large capacitance is in chip and therefore always you will write to reduce down down frequency from the higher ones and you do not want images to move through so no DC signal should go out okay so very important that it settles to a frequency exactly some other day some other time before we quit this today last introductory part which is again as I say not the part of the course but I think you should know before you quit switch capacitor circuits are very very popular in a to D converters or many of the filters okay like you can even make a ladder filter LCR filter using switch capacitors why we want to change everything to capacitance because we know the resistance and inductance are always troublesome in taking area than accuracy capacitors are well within my control so I prefer all circuits to work with capacitors so here is something very interesting let's take a case this is your resistance your voltage V1 your voltage V2 one of them is higher let's say V1 so V1 minus V2 upon R is high ohm's law or R is equal to V1 minus V2 by I or V1 minus V2 what is current charge per unit time charge per unit time but what is one upon time frequency charge is essentially Q times something and total charge will be decided by the capacitance available there some way into frequency something of this kind not exactly so I have an idea that I can replace R's a CV crown either CVC so I can replace a resistance by a capacitance this is my thinking this is what essentially it means so everyone what we do okay let us say there are two switches which are driven by Phi 1 and Phi 2 Phi 1 and Phi 2 are clocks which are what kind non overlapping okay so maybe I should draw a triangular banana check you okay actually rise time 0 near the if you want further you can do like this okay so essentially I am saying there is a dead time in which both signals are 0 both lots are 0 of course the period is same from this to this or from here to here whichever way you look at the period is same okay so here is a Phi 1 Phi 2 non overlapping clocks and let's say I have a input voltage given here V1 input output voltage expected there are actually put by me is V2 do you see it is I am trying to replace the resistance by this network is that clear V1 V2 V1 V2 which may are high I am replacing with two transistors switches and a capacitor if you have it done I will give the maths on that okay so when the Phi 1 is high and therefore Phi 2 is 0 okay so what is the charge on the capacitor Q1 is CV1 if Phi 1 is high Phi 2 is guaranteed low so Q that is the capacitor is charged to potential V1 and holds a charge of Q1 which is C1 V1 second time I close Phi 1 and make Phi 2 high so during dead time it is retaining the charge of C1 V1 after some time my Phi 2 starts the problem why I kept that time because I do not want charge to be not reaching its maximum I want that charge to be retained as the fixed value of DC which I put V1 okay now on the Phi 2 was high the charge on the capacitors from this side you can see this is V2 and this is your capacitance so this is like a switch closed okay this is like a switch open so now this tries to charge this capacitor depending on initially it will decide what the new charge should be but assuming the charge which it should go if initially there was no charge should be CV2 however it both are one by one so the net charge on the capacitor assuming C1 V1 is higher is Q1 minus which essentially is C V1 minus V2 in one clock cycle of the phase Q1 minus Q2 is the average charge current which is flowing through this charge divided by time so this is the average current which is essentially equal to C V1 minus V2 divided by T but we know from our earlier theory current is essentially V1 minus V2 by or S or whatever R switch capacitor equivalent may be we will say it the equivalent resistor have amper so V1 minus V2 by R that is the current flowing through this so if I equate this the switch capacitor is T by C or equal to 1 upon F clock so if I know my two phase clock and I know its frequency I can create a resistance of 1 upon Fc equivalently is that correct before we quit we make a simple filter so it will be C Rc time constant is C2 by C1 or C2 by C into clock okay 1 upon clock R is 1 upon Fc so if I want Rc into C2 then it is C2 by C into 1 upon F clock you can see from here I can create any filter between these capacitors and an integrating capacitance also I can put switches there any resistor I want an amplifier I replace that resistance by a capacitor switch and then the ratio of capacitance will give you gains so I can make an amplifier I can make an integrator because I do not put R there I put only C I get an integrations so I have I can create every circuit of opium which requires R can be replaced by a switch capacitor what is the advantage because capacitance are the easiest to make in MOS technologies or even bipolar technologies compared to every other resistor or any other values you want to fix okay it is partly digital because switches are there and that is where the problem started before we quit no reason to explain but this switches are not ideal okay they create hell of an issue one problem is which everyone should know whether it is digital analog circuit non-circuit if when it is on there is a charge in the channel okay when you make f0 you expect this charge to collapse so where it can collapse either at the source end or at the drain end yeah charge has to be withdrawn but there is a capacitor sitting here okay so the next value of set lege churro is co kisita saia dekhazhaya ki yeh yaan jane ke pehle ek is a kuch aur circuit so chokya bana factayen jokie so echo transistor daltayen jiska source drain short karna or is ki agar phir kappa So the final voltages are not exactly known depends on the frequency which you operate. This is another problem much probably this feed forward, feed forward, backwards problems are very difficult to solve but can be minimized. It is called Ekor method, it is called CMOS, partly solved. The third problem is KT by C noise and that KT by C noise always exist. So switches being non-ideal, the issues of non-ideality play a role in any switch capacitor systems. But otherwise they look to be very promising, they look to be very promising. Okay, so this finishes whatever I wanted to tell you in this course, not that it is enough, not that it is less but this is enough for this semester.