 Hello, and welcome to this presentation of the STM32 real-time clock. It covers the main features of this peripheral, which is used to provide a very accurate timebase. The RTC peripheral features an ultra-low-power calendar with alarms, which run in all low-power modes. Additionally, when it is clocked by the low-speed external oscillator, or LSE, at 32.768 kHz, the RTC is functional even when the main supply is off and when the VBAT domain is supplied by a backup battery. The RTC consumes only 130 nanoamps at 1.8 volt, including the LSE power consumption. The RTC is a trust-zone-aware peripheral with privilege access filtering. The hardware calendar is provided in binary-coded decimal or BCD format to reduce software load, particularly when the date and time must be displayed. Tamper detection and backup registers belong to the TAMP peripheral. The key features of the RTC are seconds, minutes, hours, weekday, date, month, and year, provided in binary-coded decimal format. Subseconds are provided in binary format. Add or remove one hour on the fly to the calendar in order to manage daylight savings. Two programmable alarms, which can wake up the microprocessor from all low-power modes. An embedded auto-reload timer, which can be used to generate a periodic flag or interrupt with wake-up capability. The resolution of this timer is programmable. The calendar can be calibrated thanks to a reference clock at the mains frequency of 50 or 60 Hz. A digital calibration circuit allowing compensation of the crystal accuracy with 0.95 ppm resolution. A timestamp function to save calendar contents and timestamp registers, depending on an external event. Here is the RTC block diagram. The RTC has two clock sources. The RTC clock, or RTCCLK, is used for the RTC timer counter. And the APB clock is used for RTC register read and write accesses. The RTC clock can use either the high-speed external oscillator, or HSE, divided by 32, the low-speed external oscillator, or LSE, or the low-speed internal oscillator, or LSI. To be functional in stop or standby mode, the RTC clock must use the LSE or LSI. To be functional in shutdown or VBAT mode, the RTC clock must use the LSE. The RTC clock is first divided by a 7-bit programmable asynchronous pre-scaler, which provides the CKA pre-clock. Most of the RTC is clocked at the CKA pre-frequency, so in order to reduce power consumption, it is recommended to set a high asynchronous division value. The default value is 128. Then, a 15-bit programmable synchronous pre-scaler provides the CKS pre-clock. The CKS pre-clock must be 1 Hz in order to update the time and date BCD registers in one-second increments. The sub-second register resolution is defined by the CKA pre-frequency. By default, it is 256 Hz, when the RTC clock frequency is 32,768 Hz. The SSR register resolution is increased by reducing the asynchronous pre-scaler value. The asynchronous pre-scaler can also be bypassed. In this case, the sub-second register resolution is defined by the RTC clock frequency. The RTC has two outputs that can provide the alarm flags, the wake-up timer flag, a calibration output from the pre-scalers, and also a tamper detection event. In this figure, the shadow registers belong to the APB clock domain. This is explained later in this presentation. The RTC offers two ways to reduce the consumption, thus increasing the battery life. The pre-scaler is split into two programmable pre-scalers. A 7-bit asynchronous pre-scaler configured through the pre-DivaA bits of the RTC pre-R register. A 15-bit synchronous pre-scaler configured through the pre-DivaS bits of the RTC pre-R register. It is recommended to configure the asynchronous pre-scaler to a high value to minimize consumption. With a divide ratio of 128, the CKA pre-frequency of its 256 Hz, which is the optimal configuration. With a divide ratio of 16, the CKA pre-frequency is 2048 Hz and consumption is increased by 30 nanoamps. With a divide ratio of 4, the CKA pre-frequency is 8192 Hz and consumption is increased by 130 nanoamps. It is possible to reduce drastically the RTC power consumption by setting the LP-Cal bit in the RTC-Cal-R register. In this configuration, the whole RTC is clocked only by CKA pre instead of RTC-CLK or CKA pre. Consequently, some flag delays are longer and the calibration window is longer. When LP-Cal is equal to 0, the calibration window is 2 power of 20 RTC clocks, which is a high consumption mode. When LP-Cal is equal to 1, the calibration window is 2 power of 20 CKA pre clocks, which is the required configuration for ultra-low consumption mode. The LP-Cal bit is ignored, assumed to be 0, when the asynchronous prescalar division factor pre-DIV-A plus 1 is not a power of 2. The RTC is a trust zone-aware peripheral. When trust zone is enabled, two protection modes are supported, global protection or per-RTC feature protection. When the DEC-Prot bit is cleared in the RTC-SMCR register, writing the RTC registers is possible only in secure mode. Calendar, security and privilege configuration registers are not read protected. All other RTC registers can be read only in secure mode. When the DEC-Prot bit is set, each RTC feature, i.e. initialization, calibration, Alarm A, Alarm B, wake-up timer and timestamp can be placed in its own hardware-enforced security domain thanks to individual protection configuration against non-secure or non-privilege access. A non-secure access to a secure protected register is denied. The same approach is used for privilege protection, either global or per RTC feature. A non-privileged access to a privileged protected register is denied. Two separate interrupt request signals report RTC events to the Cortex M33. The non-secure and the secure interrupts. By default, after a backup domain power on reset, all RTC registers can be read or written in both secure and non-secure modes, except for the RTC Secure Mode Control Register or RTC-SMCR, which can be written in secure mode only. The RTC protection configuration is not affected by a system reset. When trust zone is disabled, the APB accesses to the RTC registers are non-secure. The RTC is initialized using a safe method. The RTC registers are right protected to avoid any possible parasitic right accesses. First, the disable backup domain protection bit must be set in the Power Controller Control Register in order to enable RTC right accesses. Then, a specific sequence must be written in the RTC right protection register. Initialization mode must be entered in order to change the clock prescalar values or the calendar value. The RTC calendar keeps running in all low power modes, in VBAT mode and during reset. Initialization of the time and date registers is performed via their shadow registers, which are in the APB clock domain. The sub-second register cannot be initialized. The calendar sub-second time and date registers can be read in two different modes. When the bypass shadow registers control bit is cleared, the shadow registers are read. The advantage of this mode is that it guarantees that all three registers are consistent. Reading either RTC SSR or RTC TR locks the values in the higher order calendar shadow registers until RTC DR is read. The disadvantage of this mode is that when exiting stop, standby, or shutdown mode, the software must wait for a synchronization delay to ensure that the shadow registers are updated with the last calendar register values. This synchronization delay can be up to one RTC clock periods. When the bypass shadow registers control bit is set, the actual calendar registers are read directly. The advantage of this mode is that there is no need to wait for the synchronization delay. The disadvantage is that the read values can be false or not consistent due to synchronization issues. So they must be read twice and compared with previous read values to ensure they are correct and coherent. This slide presents the main calendar features. Daylight savings can be managed by software with automatic one hour addition or subtraction. It is possible to synchronize the RTC clock to a remote clock by adding or subtracting an offset to the sub second register on the fly with the CKA pre-clock resolution. This feature is commonly used in RF applications. A reference clock means at 50 or 60 hertz can be used to enhance long term calendar precision. The reference clock is automatically detected. When the one hertz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts the one hertz clock a bit so that future one hertz clock edges are aligned. Thanks to this mechanism, the calendar becomes as precise as the reference clock. When the reference clock is not available, the LSE clock is automatically used to update the calendar. A timestamp function is available. The sub second time and date values are saved in timestamp registers when an event occurs on the timestamp IO. A timestamp event can occur when a switch to VBAT occurs. A timestamp can also be generated when a tamper event is detected. If a timestamp event occurs while the timestamp flag is set, the timestamp overflow flag is set. In this case, timestamp registers maintain the timestamp of the previous event. The digital calibration is used to compensate crystal inaccuracy and accuracy variations with temperature and aging. It consists in masking or adding a programmable number of RTC clock cycles fairly well distributed in a configurable window. The calibration value can be changed on the fly, depending on detected temperature changes for instance. A one hertz calibration output signal is provided to measure the crystal frequency before and after applying the calibration value. The accuracy shown here is the resolution of the digital calibration. The calibration window size is configurable between 8, 16 and 32 seconds. For a 32 seconds calibration window, the accuracy is plus or minus 0.48 ppm. The total correction range is from minus 487 to 488 ppm. The accuracy resolution scales with the calibration window size. Final accuracy in the application will depend on the crystal parameter precision. Temperature detection precision, how often the software calibration procedure is launched, etc. In order to reach the precision of the calibration window, the measurement window must be a multiple of the calibration window. The calibration consumption can be reduced by setting the LP CAL bit in the RTC calibration register or RTC CAL R. In this case, the calibration mechanism is applied on CKA pre instead of RTC CLK. It is recommended to verify the RTC calibration with LP CAL equals 0 in order to have a 32 second calibration cycle. The RTC embeds two flexible alarms based on comparison with the calendar value. The alarm flags are set if the calendar sub seconds, seconds, minutes, hours or date match the value programmed in the alarm registers. The alarms events can wake up the device from all low power modes. The alarms event can also be routed to the specific output pin RTC OUT with configurable polarity. The calendar alarm sub-second, seconds, minutes, hours or date fields can be independently masked or not masked for the comparison. When the masks are used, periodic alarms are generated. In addition to the calendar and alarms, another 16-bit auto-reload counter can generate periodic events with wake up from low power modes capability. This counter cannot be read. Depending on the software configuration, the wake up timer clock can be the RTC CLK divided by 2, 4, 8 or 16 or the output of the synchronous prescalar. With the divided RTC CLK, the wake up period can be from 122 microseconds to 32 seconds when the RTC CLK frequency is 32.768 kHz. The resolution is down to 61 microseconds in this case. With the CKS pre-clock, the wake up period can be from 1 second to 36 hours when the CKS pre-clock is at 1 Hz. Several RTC events can generate an interrupt. All interrupts can wake the microprocessor up from all low power modes. The Alarm A interrupt is set when the calendar value matches the Alarm A value. Similarly, the Alarm B interrupt is set when the calendar value matches the Alarm B value. The wake up timer interrupt is set when the wake up auto-reload timer reaches 0. The timestamp interrupt is set when the timestamp event occurs. The interrupt signal used to report the event to the Cortex M33 depends on the security attribute of the unit which has detected it. The RTC peripheral is active in all low power modes and the RTC interrupts cause the device to exit the low power mode. In stop 0, stop 1, stop 2 and standby modes, only the LSE or LSI clocks can be used to clock the RTC. Only the LSE is functional in shutdown mode because this oscillator belongs to the VBAT domain. A bit is available in the MCU debug interface in order to stop the RTC counter when the core is halted for debugging. This is a list of peripherals related to the real-time clock. Please refer to these peripheral trainings for more information if needed. Trust zone, tamper and backup registers, reset and clock control, power control, extended interrupt controller.