 Hello and welcome to this presentation on the STM32 Timers. It will cover their main features, which are useful for handling any timing-related events, generating waveforms, and measuring the timing characteristics of input signals. The STM32 embeds multiple timers, providing timing resources for software or hardware tasks. The software tasks mainly consist of providing time bases, time-out event generation, and time triggers. The hardware tasks are related to IOs. The timers can generate waveforms on their outputs, measure incoming signal parameters, and react to external events on their inputs. The STM32 timers are very versatile and provide multiple operating modes to offload the CPU from repetitive and time-critical tasks, while minimizing interface circuitry needs. All STM32 timers, with the sole exception of the low-power timer, are based on the same scalable architecture. Once the timer-operating principles are known, they are valid for any of the timers. This architecture includes interconnection features and allows several timers to be combined into larger configurations. Lastly, some of the timers feature specific functions for electrical motor control and digital power conversion, such as lighting or digital switch mode power supplies. Here are the key features of the STM32 timers. All timers are based on the same architecture and are available in several derivatives listed later in this presentation. The timers mainly differ in the number of inputs and outputs they have, from a pure time-base without any IOs to an advanced control version with 9 IOs. Most of the timers feature 16-bit counters, some have 32-bit counters. Some features may not be present on the smallest timer derivatives, for example, DMA, synchronization, and up-and-down counting modes. Most of the timers can be linked and synchronized to build larger time-base timers, have a higher number of synchronous waveforms, or handle complex timing and waveforms. Within a timer, each and every channel can be configured independently as an input, typically for capture or as an output, typically for a PWM. The timers can serve as a trigger for other peripherals, for instance, to start ADC conversions or to monitor the internal clocks thanks to the interconnect matrix. This slide provides the block diagram of the medium-featured TIM-15 timer. The timer kernel consists of a 16-bit up-counter coupled with an auto-reload register to perform the counting period and a repetition counter to adjust the counter-rollover interrupt rate. The two timer channels are controlled by two capture-compare registers. The counter is fed by the clock and trigger control, also responsible for the timer chaining. Shown on the left are the input stage and the input conditioning circuitry, while on the right we have the output stage. It includes dead-time insertion for providing complementary PWM outputs suitable for half-bridge power stages. Note that TIM-XCH1 and TIM-XCH2 appear on both sides to indicate that they are both input and output capable. Finally, a TIM-XBKIN input can be used for a PWM emergency shutdown. The timer features multiple clocking options. The clock and trigger control, also responsible for the timer chaining, handles the clock for the counter. The default clock comes from the reset and clock controller, linked to one of the APB clock domains. The various timers are shared on the two APB domains to implement low-power schemes, typically one high-speed APB and one low-speed APB to limit the current drawn by the peripherals, including the timers. External timer clocking allows counting of external events, or to have a counting period externally adjusted. The clock source can be provided by other on-chip timers, using one of the four internal trigger inputs, ITR1 through ITR4. The input pins 1 and 2 can also serve as external clocks, with the option of including digital filters to remove spurious events. The external trigger input, ETR, can be configured as an external clock with a digital filter, programmable edge sensitivity, and a first basic pre-scaler stage to reduce the frequency of incoming signals, if needed. Lastly, the quadrature signals from an encoder can be processed to provide a clock and a counting direction, as described later in this presentation. This slide explains how to adjust the timer counting period. Each timer embeds a linear clock pre-scaler, which allows you to divide the clock by any integer between 1 and 65,536. This allows the counting pace to be precisely adjusted. For instance, a division by 80 will yield a precise 1 MHz counting rate when the APB clock is 80 MHz. The auto-reload register defines the counting period. In down counting mode, the counter is automatically reloaded with the period value when it underflows. In up counting mode, the counter rolls over and is reset when it exceeds the auto-reload value. An update event is issued when the counter underflows or overflows and a new period starts. It triggers an interrupt or DMA request that is used for adjusting time parameters synchronously with its period, which is useful for real-time control. This update event triggers the transfer from preload to active registers for multiple parameters, and in particular for the clock pre-scaler auto-reload value compare registers and PWM mode. An 8-bit programmable repetition counter allows you to decouple the interrupt issuing rate from the counting period, and have, for instance, one interrupt every single, second, third, and up to 256th PWM periods. This is particularly useful when dealing with high PWM frequencies. Some of the STM32 timers feature up and down counting modes. The advanced control timers, 1 and 8, and the general-purpose timers, 2, 3, 4, and 5. The counting direction can be programmed by software or automatically managed by the timer in center-aligned PWM mode. In this mode, the counting direction changes automatically on counter overflow and underflow. For a given PWM switching frequency, this mode reduces the acoustic noise by doubling the effective current ripple frequency, thus providing the optimum trade-off between the power stage's switching losses and noise. The counting direction can also be automatically handled when the timer is in encoder mode. Quadrature encoders are typically used for high-accuracy rotor position sensing in electrical motors or for digital potentiometers. From the two outputs of a quadrature encoder sensor, also called an incremental encoder, the timer extracts a clock on each and every active edge and adjusts the counting direction depending on the relative phase shift between the two incoming signals. The timer counter thus directly holds the angular position of the motor or the potentiometer. The simplest use case for a timer is to provide an internal time-base. This is commonly used by software routines either to provide periodic interrupts or single-shot timeout protection. The timer can also provide periodic triggers to other on-chip peripherals such as the ADC, DAC, and other timers. The update event from the timer, typically on counter overflow, is the usual means to have a software time-base interrupt or to trigger a periodic event. The basic timers, Tim6 and Tim7, are best suited for such a task as they are the simplest timer derivatives with no input output channel. It is also possible to generate internal timings using any other timer using compare events or using the trigger outputs on any other timer. It is possible to generate multiple timing events with a single timer using multiple compare channels. This slide describes the input capture features. Each channel can be individually configured as an input capture with a number of signal conditioning options. An input can be mapped on two capture channels, typically to differentiate rising edge from falling edge capture. The edge sensitivity is programmable and can be rising edge, falling edge, or both edges. An event prescaler allows capture of one event every two, four, or eight events. This decreases the CPU burden when processing high-frequency signals and allows the measure to be more accurate since it is performed over multiple input signal periods. Spurious transition events due to noise or bounces can be removed using a programmable digital filter. The figure shows how a signal is filtered when the filter acceptance is set to four. In the upper case, a clean rising edge capture is triggered four sampling periods after the rising edge, as one can notice looking at the internal counter value. In the lower case, a glitch causes the filter counter to be reset and the capture to happen after four successive samples at high level have been counted. Once the capture trigger is issued, the timer's counter is transferred into the capture counter and an interrupt or a DMA request can be issued. If a new capture occurs before the previous one had been read, the capture register is overwritten and an overcapture flag is set for the software to manage this condition if needed. This slide presents some more advanced capture related functions. The clear on capture mode causes a counter reset immediately after the capture has been triggered. This allows a direct measurement of the period while a traditional free running counter would require additional computation to obtain the period following the trigger. In PWM input mode, the timer is able to capture both the period and the duty cycle of an incoming PWM signal. The input signal is internally routed to two capture channels. The signal's rising edge is captured on input capture two to provide the period value with the clear on capture mode. The falling edge is captured by the capture one channel, which provides the pulse length duration. The duty cycle then simply corresponds to the ratio between input capture one and input capture two. Lastly, the timer includes an XOR function to combine the three input channels with XOR logic. This is typically used to handle the three 120 degree phase shifted signals coming from the hall sensors in electrical motors. This allows you to have a clear on capture happening on each and every edge three signals and have a capture value directly usable for speed regulation. This slide presents the output compare features. A compare event is generated when the counter matches the value of the compare register. This event can trigger an interrupt or a DMA request and can be reflected on the corresponding output pin by an output set, output reset or output toggle. The compare register can be preloaded. Preload must be disabled if multiple compare values must be written during accounting period. On the contrary, the preload mode must be preferred for applications with real time constraints since this gives a higher time margin for the software to update the compare register with the next value. The transfer from the preload to the active value is triggered by an update event when the counter overflows or underflows. The output compare mode can also be preloaded so as to allow glitchless transition from a PWM mode to a forced on or off state for instance. One pulse mode is used to generate a pulse of a programmable length in response to an external event. The pulse can start as soon as the input trigger arrives or after a programmable delay. The compare one register or CCR one value defines the pulse start time while the auto reload register or ARR value defines the end of pulse. The effective pulse width is then defined as the difference between the ARR and CCR one register values. The waveform can be programmed to have a single pulse generated by the trigger or to have a continuous pulse train started by a single trigger. One pulse mode also offers a re-triggerable option. In this case a new trigger arriving before the end of the pulse will cause the counter to be reset and the pulse width to be extended accordingly. This slide presents some of the PWM modes. The standard edge aligned PWM mode is programmed with the auto reload register defining the period and the compare register defining the duty cycle the counter being in up only or down only counting mode. A single timer can generate up to four PWM signals with independent duty cycles and identical frequency. When multiple PWM waveforms are generated by the same counter all falling edges occur at the same time hence the term edge aligned. On the contrary the rising and falling edges of center aligned PWMs are not synchronized with the counter rollover so that switching time varies with the duty cycle value. This is achieved by programming the counter in up down mode. This mode is interesting as it spreads the switching noise when multiple PWMs are generated with the same timer. This is a key feature for three phase PWM generation for electric motor drives since it allows you to double the frequency of the current ripple for a given switching frequency. For instance a 10 kilohertz PWM will generate inaudible 20 kilohertz current ripple. This minimizes the switching losses due to the PWM frequency while guaranteeing silent PWM operation. A variant of the center aligned mode is the asymmetric PWM mode where two compare registers define the turning on and off of the PWM signal. This provides higher resolution for pulse width setting since turn on and turn off times are individually defined. It also allows the generation of phase shifted PWM signals necessary to drive DC to DC converters based on the full bridge phase shifted topology. In this case the timer provides two PWM signals with identical frequency, 50% duty cycle and a phase shift varying from 0 to 180 degrees. This slide presents the combined PWM modes. This mode allows a logic combination of two PWM signals to be generated by adjacent channels, output compare 1 and 2 or output compare 3 and 4. The PWMs can be OR-ed or AND-ed to create complex waveforms. Typically this allows you to have two periodic pulses generated with any pulse width and any phase relationship value. The combined three phase mode specifically targets three phase motor control applications. In this case channel 5 of the timer can be combined with any of the three channels 1, 2 or 3 to insert a low state in the middle of a centered pattern PWM signal. This mode greatly simplifies the implementation of low cost current sensing techniques for three phase motor control using a technique usually referred to as zero vector insertion. This slide presents some more specific PWM modes where either the frequency or the duty cycle can be driven by external signals. The timer can provide variable frequency signals using an external reset signal connected either on the ETR or on the channel 1 or 2 inputs. The purpose of this mode is to provide a signal with a fixed on or off time and a continuously adjusted frequency controlled by the hardware. The timer provides control for the on or off time using the compare register while the auto reload register guarantees that the PWM will not stop if the external reset is missing thus providing a safe control in boundary conditions. This technique is used for a variety of purposes such as transition mode PFC or power factor controller for mains supplied applications and current controlled digital LED lighting. Another mode for the timer is to have the duty cycle controlled by hardware with either an on chip comparator or an off chip comparator. The PWM is operating at fixed frequency with maximum duty cycle being set by the compare register and the actual value controlled cycle by cycle. This is used for applications requiring current controlled PWMs typically for driving DC motors or solenoids. In this case a comparator monitors the peak current value into the load. As soon as the current exceeds a program threshold the comparator resets the PWM output which is then automatically restarted at the next PWM period thus providing a controlled peak current value. This slide presents the timer's synchronization features. The trigger controller allows you to cascade multiple timers in a master slave configuration. A timer can control one or more timers as the master timer or be controlled by another timer as a slave. The clock and trigger controller acts as a link between the timers. In master mode it can redirect outside the timer multiple internal control signals to an on-chip TRGO trigger output. In slave mode it gathers multiple inputs on TRGI the main trigger input coming from the external trigger pin or ETR or from one of the four internal trigger inputs ITR1 to ITR4 connected to the other TRGO outputs. Additionally the input capture one and two pins can also be used as an internal trigger typically to reset the counter. The slave and master modes can be programmed independently. A given timer can thus simultaneously be operating in slave and master modes in a cascaded configuration accepting input triggers while providing output triggers. This slide lists the various operating modes and the signals exchanged between timers. In master mode eight options are given for selecting the trigger to be sent on the TRGO output. The output can be a single synchronization pulse issued upon counter reset, counter enable which corresponds to the counter start, the update event, or the compare one match event. Alternatively the TRGO output can also transmit one of four waveforms generated including PWM signals to the other timer modules. In slave mode the timer operating mode is controlled by the TRGI input. In triggered mode the counter start is externally controlled. This mode is used for simultaneously starting multiple timers. In reset mode the counter is reset by a rising edge on the TRGI input typically for variable frequency PWM operation. A combined mode including reset and trigger can be used for re-triggerable one pulse mode generation. In gated mode shown in the figure the counter is active only while the level on the input signal is high. This signal is either coming from an input or from another timer in waveform generation mode. In this case synchronization pulses issued on reset, enabled, update or compare match cannot be used. Lastly the slave mode selection includes clock related modes such as quadrature encoder decoding or external clocking modes mentioned earlier in this presentation. This slide gives two examples of synchronized operation. The first example shows how four timers can be simultaneously started. A mechanism allows the master timer to start slightly delayed to compensate for the master slave link delay and have all timers synchronized with cycle accuracy. By combining the channels of timers 2, 3, 4 and 15 as shown it is possible to have up to 14 synchronized PWM channels. The second example shows how to create a 48-bit timer by cascading three timers. Here the update event generated on counter rollover is used as the input clock for the following slave timer. So that timer 3's counter holds the least significant 16-bits timer 2's counter holds the medium bits bits 16 to 31 and timer 15 holds the upper bits from bit 32 to bit 47. This slide summarizes the timers four main electrical motor control features. The timer includes specific PWM modes for controlling power switches. In addition to center aligned and combined three phase PWMs previously described, the timer features dead time insertion for complementary PWM generation and six step mode for driving brushless DC motors. It includes power stage protection circuitry with a dual level emergency stop mechanism to disable the PWM outputs by hardware in case of a fault. It is able to handle the most common sensors found in motor control systems. Quadrature encoders and hall sensors are used for fine and coarse position feedback while tachometer generators are used for cost effective speed feedback and just require a clear on capture mode. Lastly the timer includes synchronized ADC triggering options necessary to properly manage voltage and current sensing and avoid any acquisition issues due to switching noise in power stages. This slide presents the dead time function. A hardware dead time generator provides two non-overlapping complementary PWMs from a reference PWM signal. The STM32 timers include up to three dead time generators for OC1, OC2 and OC3 channels. The dead time duration is programmed with an 8 bit value. This value can be locked by the user to prevent this critical value from being corrupted during run time. This is done by setting a right once lock bit which switches the dead time register into read only mode until the next MCU reset. Dead time insertion is necessary when driving half bridges where a pair of transistors are connected in series between two power rails. In this case it is necessary to insert some time before the switch on of one side to allow the other side to switch off taking into account physical switching characteristics. Half bridges are usually found in DC to DC converters for DC or stepper motor drive using the full bridge topology shown here for three phase inverters with three PWM pairs. This slide shows how the six step drive also called block commutation is managed with the STM32 timer. It consists of chaining two timers, one handling the three hall sensor signals while the other manages the PWM generation synchronized with rotor angular position generating six successive steps. The first timer operates in clear on capture mode triggered by the three inputs. A compare register here compare two is responsible for adding a programmable delay between the raw angular position and the commutation time. The capture register one holds the timing interval between successive hall sensor edges and is necessary for the speed regulation loop. The compare two match event is propagated to the slave timer through the TGRO output. These events serve as commutation events and trigger changes for PWM generation. For each of the six steps of the sequence, the states of the six outputs are defined to be either forced active or inactive or generating a PWM signal. The transition from one step to the other is preloaded by software in the commutation interrupt routine and automatically transferred by hardware to reprogram the output operating mode when the next commutation arrives. The figure at right shows the six PWM signals for two consecutive complete six step sequences together with the current in one of the motor phases. This slide presents the break function. A break event triggers a hardware protection mechanism that automatically disables the PWM outputs and forces them to a user configurable state either low impedance with high or low level or high impedance. The logic circuitry works asynchronously without any clock. This guarantees the functionality even in case of a system clock failure and avoids any clock related propagation time that would tend to delay the protection. This feature is available on all timers having complimentary PWM outputs which are capable of performing power conversion tasks on timers 1, 8, 15, 16, and 17. Timers 1 and 8 have two separated break channels. This provides a dual level protection scheme where for instance a low priority protection with all switches off can be overridden by a higher priority protection with low side switches active. Furthermore a dead time delay can be inserted immediately before entering the fault mode for safely disabling the power stage. This prevents potential shoot through conditions. Let's consider for instance that the fault occurs when the high side PWM is on while the safe state is programmed to have high side switched off and low side switched on. At the time the fault occurs the system will first disable the high side PWM and insert a dead time before switching on the low side. This slide presents how the break function sources are managed. Multiple break sources can be combined for triggering a break event. Five system level sources can be selected. The core lockup Cortex-M4 internal error, the PVD or programmable voltage detector under voltage error, the SRAM parity error, the flash memory ECC error, and the clock security system or CSS indicating an external clock failure. All these features can be individually selected including the CSS. Break inputs can also be detected with the alternate function controller on the MCU pinout. Last, the two comparators and the digital filter or DFSDM can also serve as emergency shutdown sources when they detect out of range signals. External sources or on-chip comparator signals can be conditioned before entering the break detection unit. This allows selection of the proper polarity and discarding of spurious glitches by means of a digital filter. Besides the regular digital break inputs and internal break events coming from the comparators, Timers 1 and 8 feature bi-directional break inputs and outputs combining the two sources as shown in the figure. These pins combine the comparator output configured as open drain and the timer's break inputs. With a single pin, they allow global break information to be available to external MCUs and external gate drivers to shut down the inputs. This also provides the option to have an internal comparator and multiple external open drain comparator outputs to be ordered together and trigger a break event when several internal and external break inputs must be merged. This slide presents the ADC triggering options related to the timers. The ADCs can be triggered with most of the STM32 timers with three options. This can be done using compare events. The ADC conversion will start on a given compare frame. The list of supported compare events varies from one timer to the other as shown on the table. The TRGO event can also be used on certain timers. This gives extra flexibility since the TRGO can be any of the compare events or timer internal control signals such as register update, counter reset or trigger input. On the other hand, this prevents the TRGO from being used for synchronization purposes. For this reason, timers 1 and 8 also have an additional TRGO 2 output fully devoted to ADC triggering. TRGO 2 offers 16 possibilities including the six compare events and the possibility to have a dual trigger per PWM period by combining the compare 4 and 6 events. This also leaves the TRGO free for multiple timer synchronization schemes. This slide presents an example of PWM synchronized ADC trigger. For a three phase motor control, it is mandatory to have ADC readings synchronized with the PWM generated for controlling the power stage. This allows extraction of the average value out of the current waveform ripple and make sure the ADC reading is done at an adequate distance from the ringing due to the power switches. Shown here on the left is a three phase motor inverter. The six switches are controlled by three complementary PWM pairs with dead time inserted. While the current in the motor windings is measured using shunt resistors placed in the three half bridges bottom side. The right side shows the timers counter compare 1 and compare 2 values and corresponding PWM outputs for the low side switches controlled by CH1N and CH2N. The two bottom waveforms represent the current in the motor phase and the image of this current obtained on the shunt resistors. With this low cost topology the voltage can only be measured when the low side switches are on which explains the square wave shaped signal obtained on the ADC input. In this case the ADC trigger is generated on the counter rollover. This allows the reading to be done precisely in the middle of the period and get the average value of a signal with a significant ripple. Additionally, using a PWM synchronized ADC trigger also guarantees that the ADC conversion will be done away from the ringing noise present on the shunt voltages. This slide lists the interrupts and DMA requests sources. Most of the events are able to generate either an interrupt or a DMA request and even the two simultaneously. The update is issued when the counter overflows or underflows. This allows to refresh the timer's runtime settings at the beginning of the PWM period and maximize the interval before the next register update. The repetition counter allows you to skip some PWM periods and decrease the number of interrupts or DMA requests at high PWM frequency. Each of the four capture and compare events have their own interrupt and DMA. A trigger event on TRGI input regardless of the trigger source can also trigger an interrupt or DMA request. Lastly, additional sources of interrupts and DMA requests are the commutation and break events on timers 1, 8, 15, 16, and 17 only. Note that the break event does not generate DMA requests. The timer includes a DMA burst mode to have multiple registers reprogrammed with a single DMA stream. This allows the modification of several runtime parameters simultaneously, for instance duty cycle and frequency of several channels, or dynamically change the timer configuration by writing the configuration registers. The example shows how a table containing three compare values can be transferred into the compare registers with a single DMA stream when a new PWM period starts. The DMA must be programmed in memory to peripheral mode, pointing to a unique location in the timer, virtual register, Timx underscore DMA-R. When the update event occurs, the timer sends a number of DMA requests corresponding to the programmed burst length. Each value is then automatically redirected from the virtual register into the active register targeted. On the next update event, three new compare values are transferred again. In this example, this mechanism saves two DMA streams that would normally be necessary for such an update scheme. The timer is active in any of the run and sleep modes, while it is frozen in stop mode. The timer state and register content are preserved and the timer directly resumes operation when the MCU is awakened. In standby and shutdown modes, the timer is powered down and must be completely re-initialized when exiting from these modes. The timer state in debug mode can be configured with one configuration bit per timer. If the debug bit is set, the timer clock is maintained during a break point. If the debug bit is set, the timer's counter is stopped as soon as the core is halted. Additionally, the outputs of the timers having complementary outputs are disabled and forced to an inactive state. This feature is extremely useful for applications where the timers are controlling power switches or electrical motors. It prevents the power stages from being damaged by excessive current or the motors from being left in the state when hitting a break point. This slide explains how to set the timer's PWM frequency. This parameter is defined using the auto-reload value, or ARR, programmed in the TIM-X-ARR register and the clock pre-scaler programmed in the TIM-X-PSC register. The PWM frequency is given by the timer operating frequency, FTIM, divided by ARR plus 1 times clock pre-scaler plus 1. Practically, finding both register values is an iterative process where one must start from PSC equals 0. In other words, no clock division. This guarantees that the PWM will have the finest possible resolution. In this case, the ARR value is simply the ratio between the timer clock frequency and the PWM frequency, the whole minus 1. If this equation yields an ARR value above the timer's ARR range, either 16-bit or 32-bit, depending on the selected timer, the computation must be redone with a higher pre-scaler value with the following sequence. An ARR value equal to timer clock frequency, divided by 2 over PWM frequency, the whole minus 1, then an ARR value equal to timer clock frequency, divided by 3 over PWM frequency, the whole minus 1, and so on up to the point where the ARR value fits within the programmable range. This slide explains how to program a duty cycle for a given PWM frequency. This parameter is defined using the auto-reload value, or ARR, programmed in the TIMEX-ARR register and the compare value programmed in the TIMEX-CCR-X register. The duty value does not depend on the PWM frequency and is given by compare value plus 1 over the auto-reload value plus 1. Another useful indication is the PWM resolution. This gives the number of possible duty cycle values and indicates how fine the control on the PWM signal will be. The resolution, expressed in number of duty cycle steps, is simply equal to the ratio between the timer clock frequency and the PWM frequency, the whole minus 1. Another way of expressing it is in bits, as for giving a DAC converter output resolution. In this case, the resolution is the base 2 logarithm of the ratio between the timer clock frequency and the PWM frequency, the whole minus 1. This slide shows a simple practical example of PWM usage, for dimming a low power LED. This can be done directly using a PWM output, as long as the current does not exceed the rated output current. The first step is to program the frequency to be set to 1 kHz. When doing the ARR value computation with no prescalar and a timer operating frequency of 80 MHz, the value obtained is 79999, which is above the 16-bit range that can be used with timer 1. The timer prescalar must be set to 1 to have the timer operating at 40 MHz, and this results in a valid value of 3999 for the ARR register. The second step consists of computing the register value to have a 20% duty cycle. This yields a value of 7999. Lastly, the dimming resolution can be computed from formulas presented in the previous slides. With a timer running at 40 MHz, a 1 kHz PWM provides 40,000 dimming steps, which corresponds to an equivalent resolution of 15.3 bits. This slide explains a common support case, where the whole timer is configured, the PWM mode is enabled as well as the corresponding outputs, but still there's no activity on the pins. Usually this is because the MOE bit was not set. For timers equipped with dead-time generators, timers 1, 8, 15, 16 and 17, a main output enable or MOE bit in the TIMEX BDTR registers, controls all outputs, and acts as a circuit breaker in case of fault detection on the break input, global disable of all PWM outputs. The MOE bit must be set or armed to have the outputs enabled. This is valid even if the timer is used without dead-time insertion, and the timer is used for general purpose applications. The timer is linked with multiple on-chip peripherals. It serves as a trigger source for the ADC and the DAC converter. It also receives signals from the ADC's analog watch the comparator or the DF-STM filter that can be used to shut down PWM signals. This slide lists the timer instances present in the STM-32L4. Timers 1 and 8 are full-featured timers, motor control capable, including all PWM options and six compare channels for being able to simultaneously generate three-phase PWM signals and have two independent ADC triggers. Timers 2, 3, and 4 are general-purpose timers, including all PWM modes, up-down counting capability, and four channels. Timers 2 and 5 additionally offer 32-bit counting range. Timers 15, 16, and 17 are light timers with support for standard PWM only with one or two channels and up-counting mode only. They complement the other timers whenever additional independent time bases are necessary. They also have dead time insertion and break input for driving simple power systems with one PWM pair only. Lastly, timers 6 and 7 are pure time bases with no outputs, aimed principally to trigger the DAC converters or to provide software time bases. Three application notes complement the timer sections in the reference manual. AN-2592 gives a practical timer made of two synchronized 16-bit timers and is useful for better understanding the overall timer synchronization mechanism. It comes with a software example. AN-4013 provides a more detailed overview of all timer features and available firmware examples. AN-4507 presents an implementation of PWM resolution enhancement by means of dithering techniques. It comes with a software example.