 Hello, and welcome to this presentation of the STM32 Low Power Universal Asynchronous Receiver Transmitter Interface. It covers the main features of this interface, which is widely used for serial communications. The Low Power Universal Synchronous Asynchronous Receiver, or LPUART, provides full UART communications at 9600 BOD when the LPUART is clocked using a low-speed external 32.768 kHz oscillator, or LSE. Higher BOD rates can be reached when it is clocked by clock sources different from the LSE clock. Applications can benefit from the easy and inexpensive connection between devices, requiring only a few pins. In addition, the LPUART peripheral is functional in low power modes. It comes with transmit and receive FIFOs with capability to transmit and receive in stop modes. The LPUART is a fully programmable serial interface with configurable features such as data length, parity that is automatically generated and checked, number of stop bits, data order, signal polarity for transmission and reception, and BOD rate generator. The LPUART can operate in FIFO mode and it comes with transmit and receive FIFOs. It supports RS-232 and RS-485 hardware flow control options. The LPUART supports dual clock domains, allowing for wake-up from stop modes and BOD rate programming independent of the peripheral clock. The multiprocessor mode allows the LPUART to remain idle when not addressed. In addition to full-duplex communication, it also supports single-wire half-duplex mode. Here is the LPUART block diagram. The LPUART clock, LPUART KERCK, can be selected from several sources. Peripheral clock or APB clock, the system clock, the high-speed internal oscillator or HSI-16, or the low-speed external 32.768 kHz crystal oscillator or LSE. TX and RX pins are used for data transmission and reception. Pins NCTS and NRTS are used for RS-232 hardware flow control. The driver-enable or DE signal, which is available on the same IO as NRTS, is used in RS-485 mode. The LPUART has a flexible clocking scheme. Its clock source can be selected in the RCC, and it can be either the peripheral clock or APB clock, the system clock, the high-speed internal oscillator or HSI-16, or the low-speed external 32.768 kHz crystal oscillator or LSE. The LPUART clock source can be divided by a programmable factor in the LPUART PRESC register. The registers are accessed through the APB buzz, and the kernel is clocked with LPUART KERCK, pre-scaled or not, and which is independent from the APB clock. The maximum BOD rate that can be reached is 9600 BOD when the clock source is LSE, and 21 MB when the clock source is at 64 MHz. The frame format consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start bit, or S, where the line is driven low for one bit period. This signals the start of a frame and is used for synchronization. The data length can be 9, 8, or 7 bits with the parity bit counted. Finally, one or two stop bits, where the line is driven high, indicate the end of the frame. The previous slide described a standard frame. This slide shows an example of an 8-bit data frame configured with one stop bit. An idle character is interpreted as an entire frame of ones. The number of ones will include the number of stop bits as well. A break character is interpreted as receiving all zeros for a frame period. At the end of the break frame, two stop bits are inserted. The LPUART supports full duplex communication, where the TX and RX lines are respectively connected with the other interfaces, RX and TX lines. The LPUART can also be configured for a single wire half-duplex protocol, where the TX and RX lines are internally connected. In this communication mode, only the TX pin is used for both transmission and reception. The TX pin is always released when no data is transmitted. Thus, it acts as a standard I.O. in idle or reception states. For this usage, the I.O. must be configured with the TX pin in alternate function open drain mode with an external pull-up resistor. In the RS-232 standard, it is possible to control the serial data flow between two devices by using the NCTS input and the NRTS output. These two lines allow the receiver and the transmitter to alert each other of their state. This slide shows how to connect two devices in this mode. The idea is to prevent dropped bytes or conflicts in case of half-duplex communication. Both signals are active low. For serial half-duplex communication protocols like RS-485, the master needs to generate a direction signal to control the transceiver or physical layer. This signal informs the physical layer if it must act in send or receive mode. In RS-485 mode, a control line driver enable is used to activate the external transceiver control. The DE control line shares the pin with NRTS. To simplify communication between multiple processors, the LPU-ART supports a special multiprocessor mode. In multiprocessor communication, it is desirable that only the intended message recipient should actively receive the message. The non-address devices may be put in mute mode using two methods, idle line or address mark. The LPU-ART can enter or exit from mute mode using one of two methods, idle line detection or address mark detection. The LPU-ART can operate in FIFO mode, which is enabled or disabled by software. It is disabled by default. The LPU-ART comes with a transmit FIFO or TX-FIFO and a receive FIFO or RX-FIFO, each being 16 words deep. The TX-FIFO is 9 bits wide. The RX-FIFO default width is 12 bits. This is due to the fact that the receiver does not only store the data in the FIFO, but also the error flags associated to each character, parity error, noise error and framing error flags. Provided that the TX-FIFO and RX-FIFO are clocked by the kernel clock, it is possible to transmit and receive data even in stop mode. It is possible to configure TX-FIFO and RX-FIFO thresholds used mainly to avoid an underrun overrun issue while waking up from stop mode. The LPU-ART is able to wake up the MCU from stop mode when the LPU-ART clock source is the HSI or LSE clock. The sources of wake up can be a specific wake up event which is triggered by either a start bit or an address match or any received data, an RX-NE interrupt when FIFO management is disabled or FIFO event interrupts when FIFO management is enabled. This table lists the LPU-ART events that can generate an interrupt. This table lists the FIFO event interrupts when the FIFO management is enabled. The DMA requests can be generated when received buffer not empty or transmit buffer empty flags are set when FIFO management is disabled. The DMA request can be generated when the transmit FIFO not full and receive FIFO not empty flags are set when FIFO management is enabled. Several error flags can also be generated by the LPU-ART as shown in the table. The overrun, parity and framing error flags are each set when the corresponding error occurs. The noise error flag is set when a noise is detected on the received frame start bit. The LPU-ART peripheral is active in run mode. The LPU-ART interrupts cause the device to exit sleep mode. The LPU-ART is able to wake up the MCU from stop mode when the LPU-ART clock source is the HSI or LSE clock. In standby mode the peripheral is in power down and it must be re-initialized after exiting standby or shutdown mode. The STM-32H7 devices embed a single LPU-ART instance. Compared to the USART the LPU-ART doesn't support synchronous, smart card, IRDA and LIN modes. It does not support the receiver timeout, modbus communication and the auto-bod rate detection features as well. This is a list of peripherals related to the LPU-ART. Please refer to these peripheral trainings for more information if needed. General purpose input output, reset and clock controller, power controller, interrupts controller and direct memory access controller.