 Hello everyone, welcome to lecture on VHDL module for half adder and full adder. At the end of this session students will be able to analyze, design and implement half adder and full adder. Now before starting with the actual session, let's stop the video and think about what is entity. So if you know that entity is nothing but which specify the circuits IOPORTS means what are the inputs you are applying to your design or system right and what are the inputs and outputs you are having for that. So now let's start with the actual one. Let's start with the half adder. So this is the half adder right. So everyone knows that half adder which is nothing but having two inputs. Say here in 1, in 2 right and you are getting two output these those are nothing but sum and carry right. So sum you are getting with the help of you can see over here the gate is used is XOR right and carry is you are getting with the help of AND gate. So two inputs and two outputs this is the half adder. Now this table shows the true table right. So inputs and outputs sum carry. So you are because of two inputs you have four combinations 0 0 0 1 1 0 and 1 1 right. So now for 0 0 sum is 0 and carry is 0. For 0 1 sum is 1 carry is 0 and for 1 0 sum is 1 carry is still 0 and for 1 1 in that case your sum is 0 and you are getting the carry is 1 right. So now to design a VHDL module you already have a system or a design right and for that design you know what are the inputs what are the outputs right. You know the behavior of your system this one from this truth table you can easily describe how your circuit is going to work. Means when you applied which this input what will be the output you know that and that will be getting with the help of internal structure that is you have to implement using XOR gate and using AND gate right. Now let us go for the actual VHDL module writing right. So while writing the VHDL module if you are using a software like say Xiling which I have used in that while creating a project for your design you have to mention that what are the inputs what are the outputs for which device family you are writing the code right. So once you done that setting part it will pop the window in which you going to write the actual behavior in a statement or with the help of instructions right. So I will just briefly explain you actual code of your half adder right. So while writing the code the first two lines are supposed to be compulsory lines those are nothing but the you have to include the library IEEE and from that library which package you are using and from that package which components you are using that you have to mention. So here first two lines are compulsory line which is by default there if it is not there you have to write that. So library IEEE we are using and from that library IEEE we are using STD logic 1164 this is the package we are using and from that package we are using all right. So these two lines are compulsory after that comes the entity part right. So entity part entity syntax is what you have to use the keyword entity then the entity name and then is after that you have to write the port declaration in the port declaration you going to mention that what are the inputs and what are the outputs right. What is the type of that right. So here for half adder we already saw that there are two inputs two outputs so port declaration in one into are the more in type is bit right then outputs are some and carry so more is out and type is again bit right and then you have to end the entity so end keyword you have to use and then entity name whatever the name you used over here right. So same name is over here. So this entity part is done now last third part of your VHD model is important that that is architecture. In that architecture you going to write the actual behavior of your design right. So this is the architecture for the half adder. So the syntax for that is what first you have to write the keyword architecture then you have to write the architecture name of the entity name whatever you just written. So that same name supposed to be over here right. So architecture architecture name of entity name is after that your architecture begins so begin then you going to write the statements whether they are concurrent whether they are sequential. If it is sequential it comes in a process if it is concurrent it is written outside the process. So now there is no process we are using so it is concurrent statements means those all the statements which are written over here are going to be executed simultaneously or parallel execution is there. So for some from the truth table we can say that or if you know the internal structure which gate logic gate you are using for some we know that input 1 XOR with input 2 right and for carry we know that input 1 is and with the input 2. Once you done you have to in the architecture so in architecture right. So this is the complete VHD model for half adder right. Now once you done with the model creation you can verify that within as xilinx itself there is a simulator called isim which is I used. So once you simulate that to verify whether whatever the model we created it is working properly or not. So once you done the simulation from the waveform you can easily verify that one it is. So this is the actual screenshot of the waveforms which I simulated using isim simulator right. Here you can see that the inputs in 1 into these are the inputs and these are the outputs some and carry. So I tried to get all the possible combinations so in case of input 0 0 here you can see that output is 0 some is 0 carry is 0. One input is 0 and another one is 1 so 0 1 for that case sum is 1 carry is 0 again vice versa that is another input is 1 this one is 0. So again sum is 1 carry is 0 both inputs are 1 1 sum is 0 carry is 1 right. So from this simulation you can say that whatever the model you are correct we are generated that working properly as expected right. Now let us go for the full adder. Now this is the full adder right so this figure shows the full adder. Now this full adder is implemented with the help of two half adders you can see over here right. So half adder model we just created so which is having two inputs A and B output to output sum and carry but here now you are having multiples so sum is indicated with the S1 and carry is indicated with the C1 right. Another half adder is connected to previous half adder which is having two inputs again whatever the sum generated with the previous half adder connected as input another input is nothing but the C in right and the output of this half adder is nothing but the sum and one more is there carry which is named as S2. So final carry is generated with the help of this OR gate. So OR gate is having two carry generated by two half adder right. So this one is internal structure if you consider the complete block this one full adder so for full adder you are having actual connection those are interacting with the outside world those are A, B, C in and S and C. So A, B, C in are the inputs S and C are the outputs right. So for this this is the truth table you can verify that later with the help of simulation right. So because of three inputs you have eight combinations right and according that you are having output sum and carry. Now let us go for the VHDL module for full adder first two lines of compensator that is library, inclusion, library IEEE and package then comes entity part entity entity name that is full adder right. Then port declaration inputs and output ports inputs are A, B, C in which are actually having interaction with the physical world outputs are S and C that is sum and carry out type is B entity ends over here same name supposed to be here then comes architecture architecture architecture name of entity name same name we have to use we used over here. Then now here we are using two half adder so one half adder so half adder is used as a component so we have to declare the component before begin of the architecture. So component name supposed to be same as a name you generated in the previous half adder so component half adder same port declaration whatever we used in a previous half adder right end component then we require two signal as we see in a previous diagram S1, C1, C2 these are the internal signal which is now not having access to the user so we need signal then architecture begin right after that component instantiation you have to write HA1 is a one component instantiation then component name then port map then signal which are mapped with the half adder that is A, B, C, S1 and C1 so A, B are mapped with the inputs E in 1 into and S1, C1 is mapped with the output sum and carry. Second component instantiation half adder port map S1, C1 are the input for this now which is mapped with the in 1 into and S and C2 are the outputs which is nothing but the sum and carry. Then final carry we are getting from oring with the C1 and C2 so this we will get the final carry. So here we get the final sum here we get the final carry. So end architecture this is the simulation output I try to get all the possible combinations 9 1 2 3 4 5 6 7 8 8 combinations are there so you can verify that with the truth table these are the references thank you.