 Okay, so good afternoon, I hope you had an enjoyable lunch and now we will have a session about the ultralow power in the STM32U5. I have some slides here and it's the same information as you have in the sheet sheet, so you can follow it here if you like or as a reference later on. So let's get started here. So the first we'd like to mention is that the U5 comes in two versions. We have one sub-family with only LDO and one with both LDO and S&PS. And this is an internal voltage regulator and it supplies and creates the V-core voltage. So it's for the V-core domain, so it's the voltage to the core to the SRAM and some digital peripherals and as well to the flash memory. So this S&PS and LDO in the version that is called Q, it has the both. In this one you can switch between the LDO and the S&PS whenever you like on the fly. So they are in parallel. So and it's always like it started in the LDO and then you can switch over to S&PS. The advantage of the LDO is it's less noise in that one, but it consumes more current, more power. And for the S&PS it has better efficiency. And this we will demonstrate later on in the hands-on. And these two versions without Q and with Q it's important to mention that they are not pin-to-pin compatible. We will have a look into some package here later on. And also the power, a lot of the voltage that is generated from this S&PS can only be used for internal loads. So even if it's out on the pin, you cannot supply external components with this voltage. That's important as well. So if we first look to the packages here, we have the 144 pins package. And in this one you can see down on the bottom side here that the pins are actually shifted one step to the left in the Q version. So you can see here that if I assume VDD and VSS here will not be the same as here in this picture for the Q version. You see that there's one PA3 here in the corner, but here it's the VDD and VSS. So it's shifted one step to the left. And the most important to actually notice is that here on this side we have VDD as a pin number 72, I think this. But here we have VSS. So it's very, very important because they have switched the voltage supply and the ground pins. That will be the consequence of this one-step move. So just as you aware of this, that you have to take care. So you cannot just drop and replace between these two functions. And you see the same. There is some difference up here on this side and as well up here as well as some differences. So just to be aware of that. And also the same here for the 64 pins LQFP versions that it's the same as you have VSS on the Q version here and VDD on the non S&PS version. And also the VCAP here will be the VSS here. So that's important to know. If we come to the next slide here, we will talk a little bit about the run mode, the different power consumptions in this and the different ranges. And inside we have four different voltage ranges. That is for the VQR. Voltage range one is 1.2 volts and it goes from 0 to 160 MHz. The range two can only run up to 110 MHz and so on. So the lowest one is the range four that is 0.9 volts and can goes up to 24, I think actually it's 25 MHz here, could be type here. And if we look to the power consumption, we have in this table here the consumption with LDO and this one is with S&PS instead. So you see for the highest frequency performance range one. You will have almost 50% drop in current consumption. And then it goes down, as you say, it's also around 50%. And even down in range four it's even higher, so almost around 60% difference. So you can save a lot of energy if you use the S&PS. And also you can see if you go on this way from range one to range four, if you go down in your performance you can also win like 20% in power consumption for the LDO version. And here on this side I think it's almost 40% drop. So this U5 is one best in the class for the ultra-low power MCUs. It's like half of the dynamic power consumption versus the L4 and L4+. And also like it's like a third versus to the L5. And this range four is replacing the low power run mode from the L4 and L5 families. So if you go to the different European modes, we can just first have a look to this slice here. The U5 is designed to perform dynamic scenarios in autonomous mode, what we call LP BAM. And this means that it can handle the different scenarios without the MCU. So the MCU can be stopped in sleep mode. So in the traditional way, it's like working normally like in the previous legacy, a center choose that yes, you run and stop and waking up and interrupts. But now when having this autonomous mode, we can offload the core domain. And that will reduce the number of wake up sequence like these red ones. So in this case, the MCU can stay in stop mode. And the autonomous mode can do all the dynamic scenarios. So we will with this make having lower average current consumption for this U5. So that's something new that it's introduced, the LP BAM handling. And that is a way for, for example, sensor data to be transferred into the SRAM from the peripherals. And also like ADC acquisitions and DAC generations. And also, as we said from Jeff sessions, that's like I2C and SPI UR transfers can be done with this autonomous mode to the SRAM from the peripherals. We'll actually see it more in next session. For this U5 has a new architecture. There is two now digital domains, CPU domain called CD and the smart run domain SRD. And this means that this SRD can handle a staff of features when the CPU domain is stopped. So for example, here we have the core to 733 in this box here. And all this green CPU domain can go in stop mode and the smart run domain can still exist and do some peripherals transfers. So in this SRD, the smart run domain contains only a reduced setup of all the peripherals like agency 4, the DAC, as we see, SPI UR and as well as run 4. And also you can say that in run and sleep, stop 0, stop 1, the both domains are fully powered. So all peripherals are functional thanks to the GPDMA and the LPDMA. But in stop 2 mode, the CD will go in low retention, so only like a lower leakage mode. So that would be now dynamic activity possible in stop 2 mode. But in stop 2 mode, the smart run domain is fully working, so it can handle the autonomous peripherals. And that's all thanks to the LPDMA can handle that. So that makes that we can save a lot of power when you're going to stop 2 mode and still have some functions running thanks to this LPDMA. So if we go to the different modes, we have the sleep mode. And this one, the CPU is stopped. The CPU clock is turned off, but all the high speed clocks are still running. And as you see, we have the same regulator as the run mode. Functional peripheral wake up sources is like before in a way. And it's quite similar to the run mode, but just the CPU is stopped in this mode. The sleep range 4 here, as we said before, is replacing the older one, low power sleep mode. So we check the next stop modes. So this is the lowest power mode with full retention and peripheral activity, this LPBAM. So here is the same, the core is stopped, and there's now execution from the MCU. But still the high speed clocks is running, but only on the preference demand. So the core will be still stopped in this mode. We have full retention of SRAM and the peripherals registers. And we can also individually power down the different SRAM pages in all the stop modes. The 0, 1, 2, and 3. When we wake up, it will run on ASI 16 or MSI. MSI is a new clock in U5. And it can run up to 24 megahertz, but only in range 4. And also we can ultra low power mode enable this bit. You can reduce the consumption. It makes that run out will be operating in sample mode. But we need to have some care about the VDD falling slow rates. So that you have to have an ion in that mode. So here is the stop mode summary, what we have. So here you can see that in stop two, the smart run domain is active here. And also we have some dynamic control of up to 16 IOS in this stop two. You can see that the power consumption is also dramatically reduced from stop 0 and stop 1. And the wake up time, the lower you go in the stop modes, the longer time it takes to wake it up. Here we have the other standby and shutdown and VBAT modes. You can see here that still we have a lot of stuff is still working out to see internal watchdog temperature detection. And also the clocks is the LSE, we have this CSS that is the clock security system. So this one can, if they see something wrong, it can go back to another clock. So you are sure that you can wake up. And also the memories you have standby mode, you have SRAM 2, 64 GB available. And also some pull up and pull down IOS and wake up pins. And you see here also, now we're talking about the nano amps consumption in these modes. And also the wake up time is increasing. And in this one it's the VBAT, it's only, yeah. Backup voltage. So how can you now do for making lower consumption in your application? So here's some tips how we can do. We have already talked about this eye cache a little bit. So if you enable this in one way, you can enable flash prefetch. So you don't need to load or jump so much in the program execution. So that will save energy. By enabling the S&P as regulators, we see in the power consumption was much reduced. These two as I mentioned are parallel and can be selected if you need on the fly. We can power down the unused flash banks. So for example, if you're just using the half of the memory, you can power down the other flash bank to reduce the power consumption. We can also power on unused SRAM, as we will see as well in the hands-on. So that is also a way to save a lot of energy. So and also if you're not using a peripheral, you can switch off the bus clock and that will also reduce. And as usual as you're designing with low power MCUs, you can use adequate voltage scaling. And if you don't use peripherals, switch it off. So we have the different clocks here. We have the HSA external high speed from 4 to 50 MHz with this CC. So if it's a failure, it can automatically switch to HSI. And that's thanks to this clock security system. We have the HSI-16, the internal RC 60 MHz, which also is user-trimmable with some registers. This can be used as a way to wake up from stop clock sources during the stop modes. We have the 48 MHz HSI-48 that is aimed for USB that you need a quite high precision. Also for the SDMMC and random number generation. We have the clock called SHSI and that is for the secure AES co-processor. It's dedicated for that one with a second or clock with 48 MHz and quite large ether. And then we have the PLLs, free independence. And we have the LSI, both 32 GHz and 250 Hz. And this you can select via registers. If you have a look into the new MSI, it's done for the multispeed internal RC. Actually it's two output clocks that is generated, the MSI-K and the MSIS. MSIS can be selected as a system clock and the MSI-K can be selected for a kernel clock for the peripherals. And from four different clocks you can combine this. So you have 16 frequencies from 100 kHz up to 48 MHz. And I think this one here, the 3.72 is aimed for some audio frequencies. I think it's for the audio sample rates. If you have 48 kHz sample rates and 64 channels, it will be this 3.72. And all of this can also be trimmable through some registers. And here we have also the pre-scalers, so you can divide the signals so you get more frequencies you want. We have also now something called autonomous peripherals clock request. If a peripherals is autonomous, it will not impact on the core power mode. So the peripherals can make a request to have the kernel clock and then it will get some clock here. But also the bus clock request can be done in this way. And then we have a new control bits for clock gating. So for the core domain we have the SMEN, that stands for the sleep mode enable. And another one bit, that is the autonomous mode enable. And that is active for the smart line domain. So these control bits can be handled from the different stop modes. And you also need to have some attention that when it's ready, this clock will be propagated to all the enabled peripherals. So it's important that you have a well-controlled setup to reach the very best power consumption in ultra-low power modes. So you have control over these bits. And then finally the XTI. So all events can work out the system from stop 01 and 02 modes. You can select the trigger edge, which one should be active. And you have a direct link from the peripherals to the vector int table. So peripherals request the HB and APB clock. It generates an interrupt and the interrupt wakes up the device that is directly connected to the Enrich.