 Hello everyone. This video is about ARM core processor modes and states. Already in the previous video I talked about resistors. In that resistors I talked about the mode field and the state field but this video will elaborate the processor modes and states. Learning outcomes at the end of this video you will be able to list the sequence of actions taken by processor when the exception occurs. List the exceptions and its priorities in the ARM core processor. Interpret the mode and state in which ARM core processor is in by analyzing CPSR. Which are the processor modes? The processor can operate in seven different modes and the processor can operate in three different states. As I already said in the resistors video I talked about the different modes and states. So at this point I want to ask you a question that can you please list the processor modes and states. You can think on this question, can write the answer, can take some time for this for five minutes. You can pause the video and can write the answer. Thank you. I hope you have written the answer. What are the different processor modes? That is user mode, fast intra-prequest mode, intra-prequest mode, supervisor mode, abort mode and undefined mode. These are the different processor modes and what are the different states? There are three different states ARM state, thumb state and jazzy state. So let us go into the details of this. What is a mode first of all? The dictionary meaning of the mode is it is a way or a manner in which something occurs or is experienced, expressed or done. Processor mode refers to the various ways the processor creates an operating environment for itself. Processor mode controls how processor sees and manages the system memory and how the task that use it. So processor is controlling the memory and the task that in different modes different processor system memory access and tasks are going to be changed. Processor modes determine which registers are active and access write to CPSR register itself. What is the access write that we are going to see further? Each processor mode is either privileged or non-privileged. So the big category of the processor modes is privileged and non-privileged. Privileged mode allows full read write access to CPSR. Non-privileged mode allows read access to control field, only read access to control field of CPSR and but allows the read write access to condition flags. There are seven processor modes out of that six are privileged modes and one is non-privileged mode. The privileged modes are abort, fast interrupt request, interrupt request, supervisor, system and undefined. Whereas one privileged mode is the user mode. Abort, which is the privileged mode. Abort, fast interrupt request, interrupt request, supervisor, system and undefined. These all five different modes these will be the mode bits in the CPSR register and these are the abbreviations used to indicate the particular mode. For example, if abort is the mode then that is indicated by in the register. For example, R13 register is there, R13 underscore ABT will indicate that R13 register is acting in the abort mode for the abort, for the abort mode that is R13 underscore ABT. Fast interrupt request, FIQ, interrupt request IRQ, supervisor SVC, system SYS, undefined UND and user is USSR and these are the particular mode bits for this different processor modes. Now, we have seen the modes but what that what is the meaning of these modes? So, for that let us look at this. Abort mode indicates there is a failed attain to access memory. The processor enters in this mode when the interrupt occurs that is a fast interrupt request mode and interrupt request mode. Both these modes correspond to two levels of interrupts. FIQ is generated externally by taking n FIQ input weight low. FIQ indicates a fast interrupt request and it can be disabled by setting the F flag in CPSR. We already discussed the condition flags in registers and in that F flag is if we set it to one it indicates the FIQ is disabled. Supervisor mode, processor enters in this mode after receipt. Generally this mode in this mode operating system kernel operates in. We already talked about the kernel also in the software architecture of an embedded system. System mode, in system mode system mode is nothing but a special version of user mode. This mode allows full read write access to CPSR. User mode it is used for programs and applications. This is the CPSR register which has already been shown in the registers video but here also you can see these are the condition flags and these are the mode bits and every processor except user mode can change the mode bits. How we can change the mode? The mode can be changed by writing the mode bits to CPSR. Which bits these bits need to be written in the mode then the processor enters into the particular mode. Processor mode can be changed by program that writes directly to CPSR. How we can write these bits by writing the program or by hardware when the core responds to exception or interrupt? Exceptions that occur when there is receipt, fast interrupt request, interrupt request, software interrupt, data abort, prefetch abort or undefined. These are the different exceptions that occur. So that time the hardware due to the hardware the mode changes. Different priorities if these exceptions occur to which the higher priority is given. So this is the priority order. Receipt is provided with a higher priority. So software interrupt and undefined instructions are given the least priority. How the mode is changed? Changing mode on an exception. The actions made by processor when the exception occurs is first is it saves the CPSR to SPSR of exception mode. This is CPSR. You can see here this is CPSR. This is saved to SPSR of exception mode. Then saves PC to LR of exception mode. Now exception mode LR whether this is the exception mode LR? No. This is the user mode R13 LR R14 LR but the exception mode LR is this one. So these registers are changed to this exception mode registers which are indicated by underscore IRQ that because it is in the interrupt request mode. So saves PC. PC program counter to exception mode LR of exception mode sets CPSR to exception mode. Now CPSR is set to exception mode and sets PC. Now what this PC will be containing? The PC will contain the address of exception handler. Now come to the processor states. We have talked about processor modes. Now talk about processor states. What are the processor states? We already said there are three different states that is arm state, thumb state and jazzle state. And how we can set these states? So by setting the bits of t and j. When this t bit is 0 then processor is in the arm state. When t is equal to 1 the processor is in thumb state. When j is equal to 1 and t equal to 0 the processor is in jazzle state. It determines which instruction set is to be executed. There are three instruction states. Arm, thumb and jazzle. Arm state has 32 bit instructions. Thumb state has 16 bit instructions. Jazzle state has 8 bit instructions. What jazzle state is? Over 60 percent of java byte codes are implemented in hardware and rest of the codes are implemented in software. The processor states if I compare with arm and thumb when CPSR t equal to 0 arm state t equal to 1 is thumb state. The instruction size is 32 bit here it is 16 bit. Core instructions are 58 instructions are there for thumb there are 30 instruction. Most of the instructions are conditional where our only branch instructions are conditional in thumb state. Data processing access to the barrel shifter and ALU whereas data processing instructions use a separate barrel shifter and ALU instructions. Program status registers read write in privileged mode whereas no direct access is provided to CPSR in thumb mode in thumb state. Register usage there are 15 general purpose registers that can be used in arm state plus program counter whereas in thumb state eight general purpose registers plus seven high registers and plus program counter can be used in thumb state. Example of CPSR is shown now you can interpret the mode and state of the from the CPSR you can interpret the processor mode and state of CPSR. So, these are the bits which are set for CPSR from that we need to find out the processor is in which mode in which state j is equal to 0 which indicates that processor is not in the jazzle state. Now let us look at whether it is in the arm state or thumb state. So, this is T bit T bit is set to 0. So, that indicates that the processor is in arm state. Now look at the mode bits these are the mode bits these bits indicate that the processor is in supervisory. So, in this way we can find out the mode and state of CPSR and in the same way we can write the particular mode and state for processor as we know the contents of CPSR register. These are the references used for preparing this video. Thank you one and all.