 Hello everyone, I am Dr. Asha Tharnge and today we will be discussing state table and state diagram representation for JK flip-flops. At the end of this session, you will be able to represent flip-flops in terms of state table and state diagram and design VHDL module for flip-flops. These are the contents we will be covering in this session. We all know that JK flip-flop is most widely flip-flop and is considered to be a universal flip-flop circuit. The JK flip-flop is basically a gated SR flip-flop with the addition of a clocked input circuitry that prevents the invalid output condition that can occur when both the inputs of S and R are at logic 1. Figure shows the symbol of a positive edge triggered JK flip-flop. Figure J, K and clock are input and Q and Q bar are output. This is the circuit of JK flip-flop which is obtained by adding the clock input to the SR flip-flop as shown. Figure shows the characteristic table for JK flip-flop. As shown during the active edge of the clock based on the input values and the present state, next state value of the output is specified. The functioning of the JK flip-flop is also expressed by the characteristic equation as shown where the next state Q plus is given by Q plus is equal to J Q bar plus K bar Q. Here the next state value itself is the output of JK flip-flop. Now pause this video and based on the characteristic equation, try to write the state table for the JK flip-flop. Well, the state table is as shown. Based on the inputs J, K and present state Q, next state Q plus is obtained with the help of a characteristic equation as J, K and Q are three variables, a total of eight combinations are obtained. Let us now try to draw the state diagram for the state table using Moore machine model. Here the possible values of states are either 0 or 1. Therefore, there are total of two states for this flip-flop given by two circles say S0 and S1. As the output is the next state value itself, therefore when the flip-flop is in state S0, output is 0 and when the flip-flop is in state S1, output is 1. Let us now consider all the input combinations one by one. Consider the first combination as shown when the present state is 0 and input J and K is equal to 0, the next state value is the same as the present state value, therefore it remains in the same state. For the next combination, when the present state is 1 and J is equal to K is equal to 0, then there is no change in the next state and therefore it remains in the same state. Again for the next combination, when present state is 0 and J is equal to 0 and K is equal to 1, there is no state transition. Now, let us consider again the next combination, when present state is 1 and J is 0 and K is 1, next state is 0 and therefore state transition takes place. For the next combination, here the present state is 0 and now J is 1 and K is 0. The state transition again takes place and the next state becomes 1. Again for the next combination, present state is 1 and now again J is 1 and K is equal to 0. The next state value is 1 which is same as the present state, so it remains in the same state. Now, consider this combination, here present state is 0 but J is equal to K equal to 1, then the next state becomes 1, so state transition takes place. Finally, consider this last combination. However present state is 1 and both J equal to K equal to 1. The next state value is 0 that is again the state transition takes place. Thus, we can conclude that if the present state value is 0 irrespective of the value of K, when J is equal to 0, no state transition takes place and the next state is 0 only. Similarly, when the present state is 1, then irrespective of the value of J, if K is equal to 0, again no transition takes place and the next state is also 1. Also, when the present state is 0 and J equal to 1, irrespective of the value of K, the state transition takes place and next state is always 1. Similarly, also when present state is 1 and K equal to 1, irrespective of the value of J, the state transition takes place and next state is always 0. Thus, finally we can represent the state diagram of a JK flip-flop as shown. Now based on this state diagram, let us now design the VHDL module for the JK flip-flop. To design a FSM using VHDL, generally the next state logic and the output logic is implemented using the if-else statement. Each state is modelled using the case statement and the states are defined either as constants or enumerated data types. Also, a separate process block is used for next state logic and state resistor model. Let us now see the VHDL code. As shown, the JK flip-flop has 3 input ports and 2 output ports. Initially, the library IEEE is declared and all components of the package std underscore logic underscore 1164 and std underscore logic underscore arith are included. Next entity with the name JK underscore state is declared. Here, J, K and clock are defined as input ports and Q and Q bar are defined as output ports. The architecture behaviour of JK state is then defined. Now before begin of the architecture, to model the states of FSM, user defined data type named states is created having two values S0 and S1 and its objects for present state and next state are declared. Also, an additional signal Q temp is declared to hold the output value temporarily. Now after the begin of an architecture, clocked process is used where at the active edge of the clock, the next state value is assigned to the present state that is state transition takes place. This is the state resistor part of the FSM. As shown here when the clock event takes place and clock becomes 1 that is at the rising edge of the clock, next state is assigned to the present state. Also in more model, the output is also modified at the active edge of the clock as shown. Another process block is used to implement the next state logic. The output function logic can be also be implemented in another process block or it can be included in the same process block as that of the next state logic. To model the state, case statement is used. Consider the state when present state is S0. From state diagram, we can see that when present state is S0, output is logic 0. Therefore, here in the case statement when state is S0, Q temp is assigned 0 value. Also, in the state diagram when j is equal to 0, next state is S0 and when j is equal to 1, next state is S1. This is modeled using the if-else statement inside the case statement as shown. Similarly, consider the case when present state is S1. Here output is logic 1. Also, in the state S1 if k is equal to 0, then next state is S1 as shown, else next state is S0. Thus, after this, the case statement and process statement is ended. Finally, the VHDL code is ended using the end behavioral statement. Thus, in this session we have seen what is the state table, state diagram and VHDL module for the JK flip-flop using the Moore machine model. These are the references used. Thank you.