 Hello and welcome to this presentation of the STM32 HDMI CEC controller module. It covers the main features of this controller that provides high-level control functions between all of the various audio-visual products in a user environment. The HDMI CEC controller integrated inside STM32 microcontrollers provides a hardware management interface allowing an STM32 to exchange device parameters with various products in a user environment. Configurable clock sources, peripheral address, and a number of received and transmission event flags are available for this. Applications benefit from a low-pin count standard interface to exchange device parameters. HDMI CEC stands for High Definition Multimedia Interface Consumer Electronics Control. The controller complies with HDMI CEC version 1.4 specifications. It provides functions needed to interface with various audio-visual products. It consists of a CEC adapter and a CEC Advanced Peripheral Bus or APB interface. The CEC adapter provides functions such as frame decoding and checking while the CEC APB interface manages the control and status registers, data in registers and data out registers, and synchronous interrupt requests. Two clocks are available for the HDMI CEC controller, the APB clock, CEC PCLK for the APB interface, and the 32 kHz kernel clock, CEC KERCK for the CEC adapter. The kernel clock can be derived from HSE, CSI, or HSI clock sources. The supported frame format consists of a start bit followed by a header block and optionally an opcode and then a variable number of operand blocks. Header, opcode and operand blocks consist of an 8-bit payload where the most significant bit is transmitted first, followed by an end of message or EOM bit and an acknowledge or ACK bit. When a transmit command is sent, the HDMI CEC sends a start bit after the following number of nominal data bit periods of inactivity which depends on the programmed signal free time or SFT value. In the SFT equals to a zero configuration, the HDMI CEC controller automatically calculates the SFT value, ensuring compliance with the HDMI CEC standard. Otherwise, it is possible to configure the SFT value to ensure a fixed timing value. Possible values are 0.5, 1.5, 2.5, 3.5, 4.5, 5.5 and 6.5 data bit periods. The HDMI CEC controller supports two RX tolerance margin modes. First, a standard tolerance mode in line with CEC specifications plus or minus 200 microseconds on start bit rise and fall time and plus or minus 200 microseconds on the rising edge of a data bit and plus or minus 350 microseconds on the falling edge of a data bit. The second mode is an extended tolerance mode where the timing for the start bit is extended to plus or minus 400 microseconds for rise and fall transition and plus or minus 300 microseconds on the rising edge of a data bit and plus or minus 500 microseconds on the falling edge of a data bit. A received data bit, excluding the start bit, is considered invalid if the period between the rising and falling edge exceeds the tolerance margins as defined by the HDMI CEC specification. In this case, a bit timing error or BTE is issued. Or the period between falling edges exceeds the tolerance margins as defined by the HDMI CEC specification. In this case, a bit period error or BPE is issued. If a BTE or BPE error is detected, the CEC peripheral notifies the other followers and primarily the initiator by generating an error bit, a low period on the CEC line of 1.4 to 1.6 times the nominal data bit period, that is 3.6 milliseconds, nominally. A message is considered lost and therefore may be retransmitted under the following conditions. A message is not acknowledged in a directly addressed message. A message is negatively acknowledged in a broadcast message. Or a low impedance is detected on the CEC line when not expected, a line error. This slide describes the various bit timing errors during message reception. A bit rising error or BRE is set by the hardware when a rising edge is detected within a data bit outside of the RX windows configured by RXTOL. Upon BRE detection, CEC message reception is optionally aborted if bit BRE STP is set to 1 and an error bit is optionally generated on the CEC line if bit BRE GEN is set to 1. A short bit period error or SBPE is set by hardware when a falling edge is detected ending the data bit before that expected by the RXTOL margin. Upon SBPE detection, an error bit is always generated on the CEC line and reception is aborted. CEC starts waiting for the next start bit once the CEC line is idle again. A long bit period error or LBPE is set by hardware either when a rising or falling edge is detected after the maximum RXTOL margin. Upon LBPE detection message, reception is always aborted and an error bit is optionally generated on the CEC line if LBPE GEN is set to 1. Here is an overview of HDMI CEC reception interrupt events. An interrupt can be produced during reception if a received block transfer is finished or if a received error occurs. Here is an overview of HDMI CEC transmission interrupt events. An interrupt can be produced during transmission if a transmission block transfer is finished or if a transmit error occurs. The HDMI CEC peripheral is active in run and sleep modes. It is not active in stop modes but interrupts from the HDMI CEC controller cause the device to wake up from stop modes on data reception as this peripheral has a clock domain independent from the CPU clock. In standby mode, the peripheral is in power down and it must be re-initialized after exiting standby. Here is a list of peripherals related to the HDMI CEC controller. Players should be familiar with all the relationships between these peripherals to correctly configure and use the HDMI CEC interface.