The S and R Latch: Digital Electronics

The basics of how the design functions to store logic.

Category:

Education

Tags:

• sr
• latch
• part
• one

[MrDawgx1]

8 minutes. And our instructor couldn't properly explain this in a hour and a half class. Thank you, you made this so simple.

[marcalanstreeter]

@FlightSimTutorials: well recall that he is using NAND gates and not NOR gates, so if you were to check this out on logicworks (or do your own truth table) you would find that he is right that, when dealing with NAND gates (inputs S= 0 and R=0 result in invalid output) and you are right when dealing with NOR gates ( inputs S=1 and R=1 result in invalid output). So no worries, just keep an eye out for those gates.

[TheKen82815]

Praise you, man

Thanks for the teaching!

[mnthol]

1 1 is the invalid state .. not 0 0 btw .. 0 0 is the latched state

[FlightSimTutorials]

I would be a great video apart from the fact that an RS latch is undefined when S and R are both 1 respectively and not when they are both 0. Good try but to some people that may rely on this for an explanation, you better fix it with an annotation or remove the video and re-upload a correct one.

[latvian83]

Great video...