25nm Triple-Level Cell NAND

25nm TLC NAND is the densest, most cost-effective silicon storage on the planet. Watch as our director of strategic NAND marketing, Kevin Kilbuck, explains the latest breakthrough in NAND process technology and what it means to consumers.

Category:

Science & Technology

Tags:

• Micron
• IMFT
• Intel
• NAND
• TLC
• MLC
• 3-bit
• SSD
• flash

[FlumenSanctiViti]

nice presentation

[Twisted86]

The only real question I have about TLC is what kind of durability is it going to have. Unless I am wrong its 100,000 writes for SLC and 10,000 for MLC so 1000 for TLC if things stay true makes it look VERY unattractive even if it is cheaper.

I would also imagine it will be even slower as the same as above goes for speed on SLC/MLC/TLC.

Makes me think TLC will be more of a "storage" solution where our primary drives will be SLC/MLC.

[EmptyMellon]

@BCEMCOCATb Ah, excellent, thanks.

[BCEMCOCATb]

@EmptyMellon In his diagram bits are represented horizontally, and each possible state is stacked vertically. There's a formula to how many states there are for a number of bits : 2^i, where i - number of bits.

So 1 bit = 2^1 = 2

2 bit = 2^2 = 4

3bit = 2^3 = 8

All those 8 states are shown in his graph to the right for 3 bits.

[chinmaydabral]

@EmptyMellon It's showing 3 bits per cell. Bits are the 0's and 1's, that is, the digits written in a single rectangle in the diagram.

Each bit can store a 0 or a 1, so for storing 1 bit per cell (SLC), you need to be able to store two combinations (0,1). That's what's shown in the first diagram. For storing 2 bits, you need 4 combinations (00,01,10,11). Similarly, for storing 3 bits you need the ability to store 8 combinations. Only one of those combinations is in the cell at any given time.

[EmptyMellon]

Is that diagram for TLC not showing a QLC since you are showing 4 bits per cell, not 3?