Micron and Intel Announce 25nm NAND

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Uploaded by on Feb 1, 2010

Micron and Intel announce 25nm NAND, the smallest, most advanced semiconductor process technology in the world. This video features highlights from a press and analyst presentation given by Intel and Micron executives at the IMFT fab on Jan. 28, 2010.

Achieving a 25nm process allows us to double the capacity of our highest-density MLC device, enabling up to 64GB in a single package and paving the way for big developments in storage, computing, and consumer electronics. Learn what our aggressive scaling strategy means for the future of storage and the next generations of NAND.

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  • Does anyone know when 25nm Nand drives are supposed to appear in the market?

  • capacity increasing.

    sense decreasing.

    leading into trap.

  • When will the 25nm SSDs going to be lauched?

  • I'm still waiting for an answer, be that info or a "no comment"

  • You say it will enable _UP TO_ 200MB/s, and i assume you mean pr flash channel. However, this is like saying the first SATA 3Gbps harddisks could do _UP TO_ 300MB/s. It's true for the interface, but it does not say anything about the real speed of the storage medium.

    Are you able to tell anything about what the internal read, write, and erase bandwidth pr die is?

    I assume most TSOPs that will reach consumer SSDs will have 2-4 dies pr package, any rough estimates on the internal bandwidth there?

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