SNES .SPC Player on FPGA

(TRIVIA : Music comes from 15 different games. Can you name them ?)
Super nintendo music file player. Made with Altera Cyclone II FPGA on DE2 board. The S-DSP part is a full hardware Avalon component. The S-SMP part (SPC700) is SNES9X ported to Nios II. SPC files are stored in a Flash ROM.
More information : http://nova.polymtl.ca/~jevalb/

Note: there is a known bug with audio output. The default DE2 project must be loaded before this project is programmed.

Category:

Howto & Style

Tags:

• FPGA
• DE2
• SNES
• SPC700
• NIOSII
• SNES9X

[thomas997]

hey, how many bits of resolution does the DAC have on that Altera board? did you implement a ROM memory, then use the switches to select the starting addresses in the ROM? I could be wrong, but I don't think you synthesized these songs your self, you would need a whole lot of discrete filter banks to do this and I don't think that Altera board has enough resources to do this.

Regardless, nice job dude.

[Jcv32]

This altera board have a 16 bit DAC. Song are RAM save states. They are stored in a zip file on the flash rom. Switches load different files.  If you don't believe the sound is synthesized by the FPGA, look at the sources.

[Resetti64]

What are the name to these games and songs?

[Jcv32]

I added annotations with the name of games and songs.

[nomy13]

Did you use verilog or assembly/c

[Jcv32]

The S-DSP part (the sound generator) is written in VHDL. The S-SMP part (the sound and music processor) is written in C and executed on a Nios II soft processor. I wrote some custom CPU accelerators in VHDL for timers and handling. There is additional glue logic written in VHDL and a I2C config device written in Verilog.

[tyranitar87]

Chrono trigger!

[tibabo]

can do the same with SnesMusic on iPhone

[Julienfun]

@triplenippel123 Beginning

[triplenippel123]

what song is it from the castlevania 4 ost ( 1:35 ) ?

[huynhxuanan]

To Author : How do the led blink so exactly follow the music?

[Teknokrade]

NNNNNNEEEEEEEEED IT

[CodeJeffo]

@speyeker ooh come on, you don't have to be jealous. This is really amazing fpga project, but when you check the files you can see there is a lot of auto generated vhdl files - nios or mega function related. So it's really perfect chance to learn how to design something like this when you see the result and can check the sources. I wish you good luck. ... anyways jcv32 made good job.

[Biopharmer]

is the output in stereo?

[mightymax1983]

Awesome! Please give us a tutorial.

[randomshinichi]

YEAH FFVI!!!!! FFV!!!! Zelda!!!