Nexys 2 VGA controller test

Testing the vga controller I created for the Nexys 2 dev board. I'm sending a bitmap from a PC over an RS232 serial connection to MicroBlaze. The serial connection is slow which is why the image is slow to load.

Category:

Education

Tags:

• Nexys
• CPE329
• FPGA
• VHDL

[LangerJan]

Hi!

Did you use a mpmc to share RAM between MicroBlaze and VGA module? I'd be interested where you save your framebuffer data.

[ollopa1]

The Nexys 2 has some PSRAM on board. It can do short bursts of sequential read/write at a clock rate of around 80MHz, but initial addressing and crossing of row boundaries requires about 70ns of settling time. During horizontal retrace, I start the initial access, wait 80ns for the SRAM to be ready, then burst at 50MHz into a BRAM horizontal row buffer. Two full VGA frames are stored in the PSRAM.

[LangerJan]

Thanks for your quick reply.

As I can see from the video you didn't use an external oscillator. How do you catch up with a 80Mhz burst? Would an external oscillator help?

I will set my goals lower, a resolution of 320x240 is fair enough for playing monkey island ;-)

[ollopa1]

I don't. As I said above, I did it at 50MHz. The maximum you could do is limited to around 80MHz by the SRAM part. The data rate of VGA pixels is 25MHz. To get more performance, it would be possible to use a DCM to generate a 75MHz clock from the 50MHz oscillator. Even at 320x240, you'll need 76.8KB for a frame buffer, but that FPGA only has ~32K of BRAM, so you'll still external memory.

[KasperMAA]

Hi ollopa1.

Im a Nexys 2 owner myself and im trying to get a VGA controller to work. Are you using Xilinx xps_tft core or your own core as a display controller? It would be really cool if I could see your EDK project because I have a lot of problems getting the xps_tft to work properly.

[ollopa1]

I wrote my own core and memory controller from scratch, save for the vsync and hsync pulse generator which I borrowed from the Digilent reference design. There's not enough BRAM to do a full framebuffer, and the Micron memory is too slow to be used as-is. The trick is to configure the PSRAM for 128-word continuous bursts and use a little BRAM as a buffer for each horizontal line. During retrace, burst the RAM as fast as you can to full the one-line BRAM buffer.

[muralipandu]

i completed my xps tft ip intialization with nexys2 XC3S500e board from digilent, iniitalization itself took lot of time,but i was unable to display image on vga i dont want to use cf cards can i have to add any syntax or drivers in my code to display image on vga from pc to fpga through rs232 please reply where i went wrong

[NeWJadaa7]

@ollopa1 I have the Nexys 3 board with the same PSRAM. I've been trying for weeks to figure out how to do synchronous burst reads/writes to it without much success (I'm very new to FPGA development all together, very fun to learn though). Would it be possible for you to send me a copy of your code that does the PSRAM access? Or maybe just a small synthesizable demo showing how to init the PSRAM for sync burst and writting/reading a burst?

[eeppeliteloop]

Thank you for all the comments. They helped me understand a better strategy which I will try.

[chouyatingde]

@ollopa1

Hi, Ollopa1

I am working on a student project quite similar to this. Could you kindly help me with following?

How much is your resolution? and how did you configure it (PLB, DMA and /or Memory controller) to enable transfer in burst mode?

[LangerJan]

True, there is only some space for a BRAM linebuffer. I just thought that 320x240 might be better to get a full line quicker from SRAM and that a faster DCM might even help some more.

Thank you for your insights.