x64 Assembly and C++ Tutorial 5: x64 Register Set

This is the 5th tutorial and this time we're going through the x64/Intel 64 register set. This will be the final tutorial on on just theory for a while, next time we'll start coding again with our new arsenal of registers.

Big things happened in the change from x32 to x64, the new register set is much more flexible and larger. We won't go through the MMX, SSE, x87 or any other registers even though they may have been added at this point. I want to address these registers along with the extensions to which they belong, we'll look at each of the SIMD registers along with their respective instruction sets.

Turn captions on because if I notice that I've missed something or some the text is too blurry to make out, I'll supply a caption explaining.

Category:

Education

Tags:

• asm
• assembly
• x64
• tutorial
• lesson
• programming
• computer
• 64
• bit
• tute
• software
• educational
• register
• set
• intel

[leet512]

be sure to watch the 1080p version as its the most legible version.

the app that it was all a part of was called CRC... but its not a true CRC algorithm... it was just my first x64 app... I was summing bytes up in various ways and came across the trouble when I tried to restrict effects to the lower 32bits and couldn't figure out why the upper 32bits were nulled out until I watched it all in MSVC

the bits in the middle that I skip over quickly, under "Setup" and "Main Loop" aren't important

[WhatsACreel]

@leet512 Nice one leet512, you're exactly correct, Intel's Software Dev. Manual 1 at 3.4.1.1 and Programmer's Manual Vol. 1 from AMD (page 26) confirm you're suspicions. Using 32 (not 16 or 8 strangely) registers clears the top 32 to 0. I had no idea of this unintuitive behaviour but I'm sure you've saved us all from impossibly difficult to track bugs! I'll annotate the video.

[WhatsACreel]

Have a look at tutorial 4. We go through the 386/486 register set here. The register set is the same only there's no R9 to R15 and instead of RAX, RBX, RCX etc. you have EAX, EBX and ECX. SSE works fine in 32 bit mode.

[WhatsACreel]

@leet512 Some are on here twice. You're not the only one with this happening. Not sure what it is.

[leet512]

@WhatsACreel btw are some of my comments appearing twice?

I dunno if its a bug with firefox or perhaps some javascript or maybe even this packet interceptor I run or who knows what.. but I've noticed often when I comment on a video my comments appear twice in a row..

I'm wondering if this is objectively happening or just some local distortion.. does my comment that begins "be sure to watch the 1080p version" show up twice and what about the comment "kewl :)", does that show up twice as well?

[leet512]

@WhatsACreel kewl :)

[leet512]

be sure to watch the 1080p version as its the most legible version.

the app that it was all a part of was called CRC... but its not a true CRC algorithm... it was just my first x64 app... I was summing bytes up in various ways and came across the trouble when I tried to restrict effects to the lower 32bits and couldn't figure out why the upper 32bits were nulled out until I watched it all in MSVC

the bits in the middle that I skip over quickly, under "Setup" and "Main Loop" aren't important

[leet512]

hey there WhatsACreel, love your tutorials!

I just uploaded a video response related to the subject of x64 registers...

it appeared to me in MSVC as if the upper 32bits were endangered by certain operations on the lower 32bits... I couldn't find a way to clamp the operation range like one could with AL and AH.

I didn't follow it up with DebugOut tests to 100% confirm but trusted the MSVC Registers window.

curious if you have come across similar findings?

my video is at v=oqfUPs30fMU

[captainsurrey]

How many registers can I use in 32 bit mode? And can I use SSE in 32 bit mode?