DAC 2012: R&D Fellow Mike Stellfox on the emerging bottlenecks in SoC system verification

Cadence R&D Fellow Mike Stellfox leads a group of trailblazers inside Cadence. Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into production. In this interview on the floor of DAC 2012, Mike gives a brief snapshot of how innovations in debug automation have moved from the lab to the show floor; and how ad-hoc hardware-software SoC verification processes are breaking down, thus calling for more repeatable, automated solutions.

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