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Uploaded by nptelhrd on Dec 12, 2007
Lecture Series on VLSI Design by Prof S.Srinivasan,Dept of Electrical Engineering, IIT MadrasFor more details on NPTEl visit http://nptel.iitm.ac.in
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RTL is an excellent way to flesh out limitations of the syn tools.
ahshabazz 3 years ago
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RTL is an excellent way to flesh out limitations of the syn tools.
ahshabazz 3 years ago