6502Soc Vid #1

Temp Description:
This 6502SoC, a branch project from the Digital Pulse Width Analyzer Project was able to push speeds of Arlet Ottens 6502 core to 38MHz as documented on http://forum.6502.org/viewtopic.php?t=1730 . The speed limiting factor was the New Haven 640x480 5.7" TFT Display. At one point I did actually see the Display clearing like you see here but at a noticeably faster 48MHz, although it was very unreliable/non-repeatable.
In this video you will see the scope displaying the 38MHz Phase 2 to the Display (on poor 40MHz rated probes), the Display changing colors @38MHz, and the software that's shown on Mikal Kowalski's 6502 assembler.
Warnung! This is a test. This is only a test... A very successful one! :D
In the video I was going to show how I converted a M. Kowalski .65b file into a .coe file, using Arlet's bin2coeV2 converter, in order for the Xilinx Core program to make the ROM, but I had noticed that the Camera battery was running low, so I decided to just focus on the stability of high speed data transfer to the Display .

Category:

Science & Technology

Tags:

• 6502
• Verilog
• VHDL
• cores
• Xilinx
• FPGA
• Spartan 3
• XC3S400
• 6502.org
• Mikal Kowalski

[sd2snes]

How much slices/flip-flops/LUTs are used by this design on the XC3S400?