The present invention improves upon
CMP process resulting in improved planarization and thus improved
CMP has emerged as the dominant dielectric planarization method due to
its ability to reduce topography over longer lateral distances than earlier
techniques. However, CMP still suffers from pattern dependencies that result in
large variation in polished oxide thickness across typical chips, which can
impact circuit performance and yield. The present invention improves upon
CMP process resulting in improved planarization and thus improved
performance and higher yield.
The present invention relates generally to wafer polishing and, more
specifically, to a Chemical Mechanical Polishing (CMP) pad dresser used in
lapping and polishing silicon wafers in either single or double sided polishing
machines.
Chemical Mechanical Polishing (CMP) is a process that is used for the
planarization of semiconductor wafers. CMP takes advantages of the synergetic
effect of both physical and chemical forces for polishing of wafers. This is done
by applying a load force to the back of a wafer while it rests on a pad. Both the
pad and wafer are then counter rotated while a slurry containing both abrasives
and reactive chemicals is passed underneath.
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