Verilog code of amba-ahb slave RTL .Port lists of amba-ahb .Naming conventions of ports.Port declarations,
each and every signals are parameterized.Port reg/wire declaration .Local variables declaration .
Sequential block for state transition .
Combo block for state transition .
Amba-AHB slave rtl state diagram
fablous piece of technical work.
karthikajj 4 years ago
if dont mind, get me some more related videos.its great
smrithihearty 4 years ago
sheer intelligence!!!! claps to the contributor..
gladsonjerry 4 years ago
Port lists of amba-ahb,Naming conventions of ports,Port declarations,Port reg/wire declaration,Local variables declaration .sequential block for state transition,Combo block for state transition .all these topics were fablous... extremelly good
Amba-AHB slave rtl state diagram
pritvi2 4 years ago
yes ashadear you are r8. this seems to be very interesting. wish i get the full version of this video.
sathyahere 4 years ago
Nice explanation... really very usefull... i have never seen a video like this in youtube with such a neat coding explanation..
ashadear 4 years ago