Project Details: https://sites.google.com/site/gaomingxjtu/projects/tmoc
Time-Multiplexed Online Checking (TMOC) is a low-overhead online checking technique for cost-sensitive SoCs, proposed and developed by SoC Design and Test Lab at ECE Department of UCSB.
Motivation
As semiconductor technology progress toward nano-scale, increasing design complexity as well as costly production testing and burn-in make it more difficult to ensure the shipment of failure-free chips. Additional in-field failure sources such as infant mortality, soft errors, silicon aging, and electro-migration contribute to quality degradation as well. To increase in-field chip availability, online checking followed by a fault circumvention process could be a promising direction. Such a solution would result in a lower product return rate and service cost. The area overhead and performance penalties of existing online checking approaches are very significant. Thus, these online checking solutions would not be suitable for cost-sensitive applications such as most consumer electronics.
Proposed Technique
To reduce hardware overhead, we propose an online checking scheme "Time-Multiplexed Online Checking (TMOC)" that offers sufficient fault coverage with less overhead at the cost of increased fault detection latency. In TMOC, a design is partitioned into modules, each of which has its own TMOC checker. One or more embedded, field-reprogrammable blocks are used as shared checker spaces. Several TMOC checkers for different modules are sequentially and periodically mapped into a shared field-reprogrammable checker space in a time interleaved fashion.
Feasibility Study
TMOC can be applied to systems that can tolerate a certain level of fault detection latency and that implemented either solely in FPGA or in SoC/SiP with an embedded field-reprogrammable block. We have successfully implemented this TMOC scheme on a set of arithmetic circuits and Finite State Machines (FSMs) without disturbing system operations on a Virtex II Pro board. A case study on a JPEG codec design and a demonstration based on a TV-to-VGA decoder demonstrated the feasibility of applying TMOC to complex designs by employing the proposed state synchronization technique. The experiment results showed that a significant checker area overhead reduction can be achieved when the design is properly partitioned.
Implementation Cost Study
Using an H.264 decoder as the design driver, the area overheads, including the overhead caused by the lower eFPGA logic density and the module-to-checker interface overhead, were examined in detail. The experimental results showed that the TMOC technique could lead to significant chip area overhead reduction for online checking. Compared to the 100% overhead incurred by a dedicated duplex checker, the overhead of a TMOC duplex checker was only 31.34% when the checker implemented in an embedded FPGA core is shared by 62 design partitions. Note that the checker area overhead can be further decreased by using a checker scheme simpler than duplex checker or having more design partitions sharing one TMOC checker space. The study on dynamic power overhead shows a similar reduction trend. It is also shown that designers can trade fault detection latency for power hungry partitions in order to minimize the overall power consumption.
Publications
[J1] Ming Gao, Hsiu-Ming (Sherman) Chang, Peter Lisherness, Kwang-Ting (Tim) Cheng, "Time-Multiplexed Online Checking," IEEE Transactions on Computers (TC), vol.60, no.9, pp.1300-1312, Sept. 2011. (Special Issue on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems)
[C2] Ming Gao, Kwang-Ting Cheng, "Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder," ats, pp.119-124, 2009 Asian Test Symposium, 2009.
[C1] Ming Gao, Hsiu-Ming (Sherman) Chang, Peter Lisherness, Kwang-Ting (Tim) Cheng, "Time-Multiplexed Online Checking: A Feasibility Study," ats, pp.371-376, 2008 17th Asian Test Symposium, 2008.
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Line production monitoring and fault detection (normal)by departutto495 views
This technique is designed to reduce the overhead of chip area for checking the circuit errors in consumer's hand. Imagine that how cool it would be if you have an iTouch or Blackberry who can check and repair themselves automatically at an extra cost of less than 10% of the original product.
goleta06 3 years ago
o yeah！ it is very cool. Now machine can repair itself. I am wondering when we can get the machine which can update(evolve) itself.
yinzhangqi 3 years ago
WoW, that would be a big A.I. topic. Currently we are only at the point to make machines 'survive' at the end of Moore's era, which is far from making them 'live' by themselves.
goleta06 3 years ago