Phase Lock Loops 101 with Bil Herd

Bil explains the basics of Phase Lock Loops(PLLs) and their uses.

Bil's youtube channel http://www.youtube.com/user/BilHerd

Category:

Education

Tags:

• pll
• analog
• Bil Herd
• Jeri Ellsworth
• Phase
• Lock
• Loop
• Phase Lock Loop
• electronic
• frequency synthesis
• clock recovery
• jitter
• loop filter

[CampKohler]

Will it do any good to bug you about the diode video, or should we just regard you as a "component tease."

[jeriellsworth]

@CampKohler I can only do videos as I have time. The ones that pay the bills get top priority followed by contract work that pays the bills. :)

[WisdomVendor]

where and when was this streamed live? and when is the next similar live stream?

[jeriellsworth]

@WisdomVendor This was from my hack lab. I do these from time to time. You can find out about the next one if you follow me on twitter.

[engmustafa83]

let us see your nice right eye

remove your hair a bit

hhhhhhhhhhhhhh

thanks a lot for this nice video

it's great

[jeriellsworth]

@engmustafa83 My hair was misbehaving. Time to get it trimmed.  :)

[RobRichmondRPG]

We need to set up a fund to get Bil a decent quality webcam ;)

[Orthosonic]

Major epic awesomeness!!!

I am a happy subscriber.

[FrankenPC]

WOW this video has been illuminating! Now I look at microcontrollers which say "80 mhz PLL" and I know EXACTLY what it means! I had no idea before! Thanks!

[rptj19]

Excellent video !

[fingerboy18]

Always account for unused states! That's good design practice :)

[josh2utube]

Great job, PLL's have always had a bit of unexplained magic... no more!

[AmazGraz]

I do well at this point to calculate the charge on a capacitor, or the RC constant. And if you have points 1 & 2, & these are through an RC network and points 3,4 for output (in an H configuration, I have trouble understanding why the output current is through 3,4. I don't see it happening. It just looks like the electricity goes between 1,2 to charge the capacitor and discharge . I mean, the simplest stuff sometimes throws me. But y'll awesome. & I gotta watch.

[chipos81]

This was excellent! Nice work, Bill. Definite yes to starters FPGA design idea.

[Vlakpage]

@RobRichmondRPG decent webcam doesn't help in 360p

[Frank55]

In my experience the design of a PLL loop filter is rather complicated. During my experiments the average frequency produced by the PLL was always right, but generally there was a lot of jitter on the signal. Especially when I used it in a synthesizer configuration to produce a VHF signal, with a 100 KHz. frequency as reference. When you listened on an SSB receiver, you could hear that the VHF frequency was constantly drifting around the desired frequency, so there was never a stable 'lock'.