ET4293.200910.Q3 Digital IC Design - Steps for Delay, Slew, and Power Check

ET4293.200910.Q3 Digital IC Design - Steps for Delay, Slew, and Power Check

Steps for Delay, Slew, and Power check:
1: Open analog environment window.
2: Run the simulation for power measurement.
3: Go to "Session -- Save Script".
4: Enter file name: "./oceanScript.ocn", and click on OK.
5: Open a new terminal as follows:
5.1: tcsh
5.2: cd your_area/proj2010/cell_design/
5.3: source sourceme
6: Open OCEAN platform and load analysis script as follows:
6.1: ocean
6.2: load("/opt/cad/cadence/DesignKits/ENS/ET4293/200910.Q3/TB_ProjTtoB_Check.ocn")
7: Open result file and note following; vim TB_ProjTtoB.log
7.1: All signals are correct or not




7.2: Average Power
7.3: Maximum Slew
7.4: Maximum Delay
7.5: Signal / Delay / Slew at every clock transition

Category:

Education

Tags:

• ET4293 Steps for Delay
• Slew
• and Power Check