FPGA Frogger

Frogger clone implemented on a Xilinx Spartan 3 FPGA
by Schuyler Eldridge and Ashley Ferrel

Final Project for Boston University EC 551 - Advanced Digital Design in Verilog

Includes 3 bit VGA output, PS/2 keyboard input, just-in-time pixel calculation (no frame buffer), pseudo random obstacle generation, and 30x30 sprites with transparency stored in FPGA block RAM. The vga output is 640x480 with a refresh rate of 60Hz.

Category:

Science & Technology

Tags:

• fpga
• frogger
• ec551
• boston
• university
• logic
• digital
• design
• verilog

[FOODFORTHEBEES]

how much did it cost you to create this?

[1705char]

@FOODFORTHEBEES It uses the now discontinued Spartan 3 Starter Kit from Xilinx (about $100), but provided by the university. Other than, that, it depends on how much I value my time... about 48 - 60 hours of work, total.

[nicksssl]

yea dude! awesome! can i see the code for that? I'm in an intro digital logic and systems course, and we are being introduced to verilog. Need some inspiration for a project...