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Good, Bad, and Useless Verification

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Uploaded by on Dec 9, 2011

Guests: Himanshu Bhatnagar, Executive Director, ASIC Design, Mindspeed Technologies

Host: Karen Bartleson, Sr. Director, Community Marketing, Synopsys

Verification is often considered the bottleneck in chip design. Himanshu talks about how to alleviate this bottleneck, what new methods are available for System-on-Chip, and what the EDA industry can do to simplify verification.

This show was originally streamed live to the Synopsys Facebook page at the 48th DAC.

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