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OZ-3, a 32-bit RISC made in Logisim

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Uploaded by on Aug 15, 2009

Links:
The .circ file: http://www.mediafire.com/?m2zhjlqz4zl
My development blog: http://benoztalay.wordpress.com
The instruction set: http://www.mediafire.com/?txeqcgl2695f8qz

I've been working on this processor throughout the summer, and I've finally finished it. It's a 5-stage RISC (instruction fetch, instruction decode, execute, memory and I/O, and writeback). Unfortunately, it doesn't have any forwarding capabilities or branch prediction, or anything of the sort. I hope to add these in at a later time, but school is starting soon and I think it's more important to see what this processor is capable of. It has 16 input pins, 16 output pins, a 32-bit input port, and a 32-bit output port for data transfers. Its ALU can perform addition, subtraction, AND, OR, XOR, and shift and rotate operations. As of yet, I haven't done much on the mathematical side of the processor, just seeing what it can do with input/output. I'm planning on making a few programs that are more math-intensive.

The program you see it running is one that takes three input pins, and according to which is '1', it displays a 0, 1, or 2 on the 7x7 LED matrix display. I've created my own display memory because the device didn't have any built in. Also, this is running at 512 Hz. If I run the clock any faster, Logisim crashes.

To program the OZ-3, I made a simple "assembler" that takes in 32-bit binary instructions and converts them to hex for use with Logisim. I tried making an actual assembler, but that turned out to be a giant hassle and I just wanted to get programming. I've also made other programs, such as one that displays one of four animations on a 7-segment display according to which input is '1'. Also, its first functional program was one where it took input from an input pin and displayed it on an output pin. Not very groundbreaking, but pretty exciting for me.

So, that's my processor! If you're wondering about the OZ-1 or OZ-2, they were both processors made in Logisim, 8-bit and 16-bit respectively. I never did finish the OZ-2, but they were both single-cycle processors with extremely limited capabilities and ISAs that were vastly too complex. Between the OZ-2 and the OZ-3, I did a fair amount of research that included a book called Processor Architecture, read cover to cover, and parts of a course on computer architecture that was on Youtube.

Thanks for viewing!

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Science & Technology

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Uploader Comments (Boztalay)

  • This is quite an amazing job there. Did you design the WHOLE thing by yourself?

  • @NerdTronX

    That I did

  • hey is there any chance to get an opcode listing, because you've uploaded the logisim file, now I'm trying to write some simple programs, but without an opcode list it's difficult..

  • @chris11119

    Hey, sorry about that! I'll get a .xml file that corresponds to that version of the OZ-3 up sometime in the next couple of days. I've since added instructions, split them up, or renamed them because of details of implementing it in an FPGA.

  • @chris11119 Hey, I uploaded the instruction set to rapidshare. I hope it's the correct version. Let me know if you have any questions or there are any problems

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All Comments (25)

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  • sorry. i was wrong.

    good work, man)

  • Its seems like another copy from book called Computer Architecture. A Quantitative Approach. Heh :) But still, great work man!

  • @Boztalay

    i thank you very mutch

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