Encounter Timing System

Encounter® Timing System offers a consistent, integrated static timing analysis (STA) environment for place-and-route optimization and signoff verification. This leads to faster convergence and design closure, and it gives designers the flexibility to use Encounter Timing System as a standalone solution or as part of the integrated SoC Encounter™ RTL-to-GDSII system. Encounter Timing System is endorsed by leading foundries, ASIC suppliers, and design companies around the world.

Category:

Howto & Style

Tags:

• timing
• analysis
• signoff
• sign-off
• signal
• integrity
• SI
• encounter
• TSMC