$49 FPGA board with 500 MBytes/sec IO bandwidth

$49 Avnet Spartan 3A FPGA evaluation board with added dual Ethernet Gb PHY daughter card.
500 MBytes/sec of IO bandwidth across 4 full duplex 125 Mhz channels. Two rx channels and
two tx channels. Each channel interface to the MACs in the fpga using RGMII DDR interface.
Each channel bit is running at 250 Mbits/sec data rate. More info at www.chipenet.com

Category:

Science & Technology

Tags:

• FPGA board
• RGMII DDR interface.

[balefrost]

I'm just an electronics beginner, but I was surprised that you wire-wrapped the daughter card to the mainboard. Would a 40 pin socket be a bad idea at those frequencies, or did you use wire-wrap for flexibility?

[ChipEnet]

@balefrost It's wire wrapped & then soldered. The 1st version didn't have the headers

but I found it didn't matter. The header & wirewrap made it easy to assemble. The

short distance is the key to making it work.

[ChipEnet]

The secret is a zoom inspection stereoscope. It lets me see the details & then

it's not so hard.  I wear glasses & my hands shake without a prop. I'll do a

video on how to hand solder fine pitch SMT & BGA parts.

[ChipEnet]

Stay tuned for the $29 FPGA board with 750MBytes/sec IO bandwidth

[soclt]

Really cool implementation! Would be awesome if the source would be open :)

[ChipEnet]

I'm not sure what you mean by the source. The board just follow the vendor's recommendation. Gb MAC is available on OpenCores. No magic here, just

an illustration.

[narcoti]

you have some nimble fingers, even though I know how to do this, I wouldn't be able to, my hands shake too bad, I envy you.

[tuxicle]

I did a board recently that needs approx. this much bandwidth (runs I/Os at 100 MHz) on a Spartan3E, but I chickened out at the last minute and made it controlled impedance (at great expense). Nice to see that just a bunch of wires performs admirably :) If you can borrow one, try looking at the signals with a FET probe rated at > 1GHz, things may not look so clean.

[metallfluss]

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