ChipEnet IEEE1588 clock

Video of ChipEnet IEEE 1588 slave clock locking to master clock under
1. steady state condition
2. sudden change in master clock frequency, increase in frequency by 1.5Mhz
3. random delay of 50% of sync packets by over 100us

IEEE 1588 is a protocol for synchronizing clocks in an Ethernet network. This video shows
the ChipEnet IEEE 1588 clock IP core performance under different conditions.

Test setup consists of 2 Xilinx Spartan 3E FPGA boards connected by 100Mb Ethernet.
One board serves as the master clock and the other board contains the slave clock servo.
Master clock is driven by 50Mhz crystal oscillator
Slave clock is driven by 25Mhz PHY clock

Top trace is RX_VLD of sync packets received at slave FPGA board
Middle trace is 32ns pulse decode of slave clock at slave FPGA board
Bottom trace is 32 ns pulse decode of master clock at master FPGA board

Category:

Science & Technology

Tags:

• IEEE 1588 protocol clock