This is a video of experimental hardware at the Institute of Neuroinformatics at ETH Zurich - The Synaptic Processing Unit, an FPGA implementing 8k Binary Cascade Synapses (Fusi et. al.) feeding into an aVLSI IFWTA Neuron Chip, forming one coherent Neural System (In this case, one output neuron sourcing from 256 input synapses) through an AER bus. The output Neuron receives a poisson input to all its randomly uniformly potentiated or depressed synapses. Here, the top trace is the membrane potential of the IF Neuron, the bottom trace are the spikes that the neuron receives from its synapses (i.e. a 'masked' version of the original input, since some synapses are depressed and do not forward spikes). Plasticity/Learning is implemented using a novel learning rule we call STADP (Spike Timing and Activity Dependent Plasticity). In this video, the input stimuli are collectively too weak to continuousely activate the output neuron, and synapses will become depressed, gradually. This is reflected in the drop of the output neuron's firing rate
In this video, the neural input is not of high enough activity and the synapses inhibit connections between input and output neurons. So basically, there is no or only a weak stimulus, and the connections 'die out' due to STADP - which is activity dependent, and the output neuron is inactive.
anthonyhsiao 3 years ago