Google Tech Talks
February, 21 2008
ABSTRACT
It is will be too costly to design many of these chips at the polygon
or even gate level, so they must be highly programmable. Furthermore,
they shoul...
Google Tech Talks February, 21 2008
ABSTRACT
It is will be too costly to design many of these chips at the polygon or even gate level, so they must be highly programmable. Furthermore, they should not just be FPGAs as we now know them because with that many transistors, we should specialize more for power efficiency. I envision FPGA-like chips where the computational elements combine CPUs with more traditional FPGA-like fabrics.
For embedded real-time applications, which I argue will dominate, I argue that the temporal behavior of these processors should be as easy to analyze and control as their functional behavior.
I present a vision such a precision-timed (PRET) processor, which incorporates a variety of techniques. At the ISA level, it provides cycle-accurate timers, a predictable memory hierarchy based on scratchpad memories, and an interleaved pipeline that provides predictable, hardware-efficient concurrency. It will be programmed in a C-like language that includes user-specified timing constraints and concurrency, perhaps with synchronous semantics. Both compile- and run-time checks will ensure the program meets timing constraints, similar to array bounds checking.
Speaker: Stephen A. Edwards Stephen A. Edwards received the B.S. degree in Electrical Engineering from the California Institute of Technology in 1992, and the M.S. and Ph.D degrees, also in Electrical Engineering, from the University of California, Berkeley in 1994 and 1997 respectively. He is currently an associate professor in the Computer Science Department of Columbia University in New York, which he joined in 2001 after a three-year stint with Synopsys, Inc., in Mountain View, California. His research interests include embedded system design, domain-specific languages, and compilers.
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The general thesis is pretty flawed: You'd have to eliminate out of order processing, reduce superscalar execution to predictable conditions, & know where the data you are accessing is located ahead of time. If you want to enforce rigid constraints you just drag performance down to a slowest common denominator, its all missed opportunity for speed. Go to 42m, theres a 10s slide showing many of these dilemmas in bullet point form: the problem is caches & pipelines and packet switching.
the guy has absolutely no idea what terms like "mathematically chaotic" mean. Not speaking about the problem of algorithmic determination of whether a Turing machine will stop on empty input or not and other basic stuff...
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In addition the embedded world is very different than the area Intel plays in. Also FPGAs are pretty expensive for the embedded world.
I wonder what could be done with 100 simple CPUs?
Even more interesting is what we would want to do with 10^12 transistors... Is excel or word going to be a good application for such hardware?
Not speaking about the problem of algorithmic determination of whether a Turing machine will stop on empty input or not
and other basic stuff...