FPGA Terasic DE0 with a verilog framebuffer application

FPGA Terasic DE0 evaluation board showing a framebuffer application. This allows the user to upload (via 115.2k serial connection) a specially formatted image in 640x400 into the DRAM memory located onboard. Once this image has been uploaded, it is then displayed on a standard VGA monitor. This initial verilog code will serve as a base of a more complicated scan-converter for a Commodore Amiga.

This incorporates a DRAM memory controller, a UART, a VGA horizontal and vertical sync generator, a seven segment driver, PLL, and a M9K dual-port RAM. More complicated than it would at first seem.

Category:

Science & Technology

Tags:

• Altera
• Cyclone III
• FPGA
• Terasic
• DE0
• diy
• electronics
• framebuffer
• frame buffer
• vga
• memory controller
• UART
• graphics
• verilog
• pll

[kmonyt]

Thanks for the comments. Yes, I did see the pads for the serial connection. Between not having a serial port on most of my (new) machines, and having the USB-TTL dongle handy, it was a no brainer. I literally just have one pin (tx to the fpga board) and ground hooked up. The converter will do 3mbps, but I'm running it at 115.2kbps.

[bigboytemp]

Oh, I see, you have an FTDI USB to RS232 dongle... Clever :-) (and much faster transfer speed!)

[bigboytemp]

Nice project. I was thinking of getting a DE0 or DE1 eventually...

One question though, why didn't you use the RS232 built-in on the DE0? I guess you did not want to mess with soldering a connector to the board, and because you already had a readily available RS232 dongle (for those who don't know DE0, you have RS232 built-in, but no DB9 connector on the board, but the board have provision to solder a 5-pins header, which you then can connect some fly-cable to a standard DB9 connector).