Digital Pulse Width Analyzer: New Hardware Design

This new build is a total redesign using all 3.3V parts and a new 640x480x18 Newhaven display with an 8-bit interface that I started back in June 2010. An attempt is made to keep chip count low.

It incorporates a WDC65C02 8-bit CPU, an XC2S15 7.5ns Spartan 2 FPGA, a 10ns 2Mx8 asynchronous static RAM, and an 200ns 512Kx8 EEPROM. Unlike the previous versions of the Digital PWA, this one has the ability to change 6502 Phase2 clock speeds "on the fly" by software control, without resetting the 6502. A 1-bit write only port is used to select between 2.5MHz and 20MHz. 2.5MHz for when the slow EEPROM is being copied to RAM, or 20MHz when the system is running from the SRAM. Note that more bits could easily be added to select more speeds.

In this video I show the memory map, the O'scope displaying Phase 2, the board itself, and the EEPROM being programmed with a routine that first writes a color test pattern to the 2Mx8 through a 16K window (although incorrect algorithm). Then the 6502 reads from the 2M ram through the 16K window and sends the data to the display. When you see the display being written to, that is 640x480x3=almost 1 million bytes!

Category:

Science & Technology

Tags:

• 6502
• newhaven display
• banked ram
• banked eeprom
• 20MHz
• digital pulse width analyzer
• 8-bit cpu